diff mbox series

[RFC,28/28] drm/i915: Enable dropping small cores when not enabled

Message ID 20210414115028.168504-29-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New
Headers show
Series Old platform/gen kconfig options series | expand

Commit Message

Tvrtko Ursulin April 14, 2021, 11:50 a.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/Kconfig.platforms | 7 +++++++
 drivers/gpu/drm/i915/i915_drv.h        | 8 ++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms
index 4208222b2aaf..9884ccb7af26 100644
--- a/drivers/gpu/drm/i915/Kconfig.platforms
+++ b/drivers/gpu/drm/i915/Kconfig.platforms
@@ -152,11 +152,15 @@  config DRM_I915_PLATFORM_INTEL_IVYBRIDGE
 	help
 	  Include support for Intel Ivybridge platforms.
 
+config DRM_I915_LP
+	bool
+
 config DRM_I915_PLATFORM_INTEL_VALLEYVIEW
 	bool "Intel Valleyview platform support"
 	default y
 	depends on DRM_I915
 	select DRM_I915_GEN7
+	select DRM_I915_LP
 	help
 	  Include support for Intel Valleyview platforms.
 
@@ -184,6 +188,7 @@  config DRM_I915_PLATFORM_INTEL_CHERRYVIEW
 	default y
 	depends on DRM_I915
 	select DRM_I915_GEN8
+	select DRM_I915_LP
 	help
 	  Include support for Intel Cherryview platforms.
 
@@ -203,6 +208,7 @@  config DRM_I915_PLATFORM_INTEL_BROXTON
 	default y
 	depends on DRM_I915
 	select DRM_I915_GEN9
+	select DRM_I915_LP
 	help
 	  Include support for Intel Broxton platforms.
 
@@ -211,6 +217,7 @@  config DRM_I915_PLATFORM_INTEL_BROXTON
 	default y
 	depends on DRM_I915
 	select DRM_I915_GEN9
+	select DRM_I915_LP
 	help
 	  Include support for Intel Geminilake platforms.
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6f56f3a42cd1..b6b98de675b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2767,9 +2767,13 @@  intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN10(p) IS_GENx(p, 10)
 #define IS_GEN11(p) IS_GENx(p, 11)
 
-#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
+#define IS_LP(dev_priv)	(IS_ENABLED(CONFIG_DRM_I915_LP) && \
+			 (dev_priv)->info.is_lp)
+#define IS_BC(dev_priv)	(!IS_ENABLED(CONFIG_DRM_I915_LP) || \
+			 !(dev_priv)->info.is_lp)
+
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
-#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
+#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && IS_BC(dev_priv))
 
 #define ENGINE_MASK(id)	BIT(id)
 #define RENDER_RING	ENGINE_MASK(RCS)