diff mbox series

[06/11] drm/i915/xelpd: Fallback to plane stride limitations when using DPT

Message ID 20210414155208.3161335-7-imre.deak@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/adl_p: Add support for Display Page Tables | expand

Commit Message

Imre Deak April 14, 2021, 3:52 p.m. UTC
From: José Roberto de Souza <jose.souza@intel.com>

GTT remapping allow us to have planes with strides larger than HW
supports but DPT + GTT remapping is still not properly handled so
falling back to plane HW limitations for now.

This patch can be dropped when DPT + GTT remapping is correctly
handled but until then we need this limitation for all display13
platforms to avoid pipe faults.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c      | 15 +++++++--------
 .../gpu/drm/i915/display/intel_display_types.h    |  8 ++++++--
 2 files changed, 13 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 00621ccea2c40..ce685a7ba6a1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1588,14 +1588,13 @@  u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
 	 *
 	 * The new CCS hash mode makes remapping impossible
 	 */
-	if (!is_ccs_modifier(modifier)) {
-		if (DISPLAY_VER(dev_priv) >= 7)
-			return 256*1024;
-		else if (DISPLAY_VER(dev_priv) >= 4)
-			return 128*1024;
-	}
-
-	return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+	if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+	    intel_modifier_uses_dpt(dev_priv, modifier))
+		return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+	else if (DISPLAY_VER(dev_priv) >= 7)
+		return 256 * 1024;
+	else
+		return 128 * 1024;
 }
 
 static u32
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3c73737f88da4..cdc8fcb8c2aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1976,10 +1976,14 @@  intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
 		intel_wait_for_vblank(dev_priv, pipe);
 }
 
+static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
+{
+	return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
 static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
 {
-	return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
-		fb->modifier != DRM_FORMAT_MOD_LINEAR;
+	return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 }
 
 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)