diff mbox series

[2/5] drm/i915/display: Replace intel_psr_enabled() calls by intel_crtc_state check

Message ID 20210418002126.87882-2-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/5] drm/i915/display: Fill PSR state during hardware configuration read out | expand

Commit Message

Souza, Jose April 18, 2021, 12:21 a.m. UTC 
All of this places don't need to intel_psr_enabled() that will lock
psr mutex, check state and unlock.

Instead it can directly check PSR state in intel_crtc_state, the only
place that was not possible was intel_read_dp_vsc_sdp() but since
"drm/i915/display: Fill PSR state during hardware configuration read
out" it is possible.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

Comments

Sripada, Radhakrishna May 10, 2021, 11:47 p.m. UTC | #1 
On Sat, Apr 17, 2021 at 05:21:23PM -0700, José Roberto de Souza wrote:
> All of this places don't need to intel_psr_enabled() that will lock
> psr mutex, check state and unlock.
> 
> Instead it can directly check PSR state in intel_crtc_state, the only
> place that was not possible was intel_read_dp_vsc_sdp() but since
> "drm/i915/display: Fill PSR state during hardware configuration read
> out" it is possible.
> 
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5ee953aaa00c..72bcc10cae4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2861,7 +2861,6 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  			     const struct drm_connector_state *conn_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
>  	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
>  			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
> @@ -2870,7 +2869,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  
>  	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
>  	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> -	if (intel_psr_enabled(intel_dp))
> +	if (crtc_state->has_psr)
>  		val &= ~dip_enable;
>  	else
>  		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
> @@ -2885,7 +2884,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>  	intel_de_posting_read(dev_priv, reg);
>  
>  	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> -	if (!intel_psr_enabled(intel_dp))
> +	if (!crtc_state->has_psr)
>  		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
>  
>  	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
> @@ -3012,14 +3011,13 @@ static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
>  				  struct drm_dp_vsc_sdp *vsc)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> -	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	unsigned int type = DP_SDP_VSC;
>  	struct dp_sdp sdp = {};
>  	int ret;
>  
>  	/* When PSR is enabled, VSC SDP is handled by PSR routine */
> -	if (intel_psr_enabled(intel_dp))
> +	if (crtc_state->has_psr)
>  		return;
>  
>  	if ((crtc_state->infoframes.enable &
> -- 
> 2.31.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5ee953aaa00c..72bcc10cae4f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2861,7 +2861,6 @@  void intel_dp_set_infoframes(struct intel_encoder *encoder,
 			     const struct drm_connector_state *conn_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
 	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 			 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
@@ -2870,7 +2869,7 @@  void intel_dp_set_infoframes(struct intel_encoder *encoder,
 
 	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
 	/* When PSR is enabled, this routine doesn't disable VSC DIP */
-	if (intel_psr_enabled(intel_dp))
+	if (crtc_state->has_psr)
 		val &= ~dip_enable;
 	else
 		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
@@ -2885,7 +2884,7 @@  void intel_dp_set_infoframes(struct intel_encoder *encoder,
 	intel_de_posting_read(dev_priv, reg);
 
 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
-	if (!intel_psr_enabled(intel_dp))
+	if (!crtc_state->has_psr)
 		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
 
 	intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
@@ -3012,14 +3011,13 @@  static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
 				  struct drm_dp_vsc_sdp *vsc)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	unsigned int type = DP_SDP_VSC;
 	struct dp_sdp sdp = {};
 	int ret;
 
 	/* When PSR is enabled, VSC SDP is handled by PSR routine */
-	if (intel_psr_enabled(intel_dp))
+	if (crtc_state->has_psr)
 		return;
 
 	if ((crtc_state->infoframes.enable &