From patchwork Wed Apr 21 16:48:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 12216563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46154C433ED for ; Wed, 21 Apr 2021 16:49:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 887DE61454 for ; Wed, 21 Apr 2021 16:49:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 887DE61454 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E5E6E6E9A6; Wed, 21 Apr 2021 16:49:09 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 752916E9A6 for ; Wed, 21 Apr 2021 16:49:09 +0000 (UTC) IronPort-SDR: SfwflnN6ZLPvBRgDukIaUINyMk+TTzWueqS/Db3AkJH2I6xbloTMVkOTwPiEw2afZNZDYZ5ZXl ej10SIsUg41A== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="195846094" X-IronPort-AV: E=Sophos;i="5.82,240,1613462400"; d="scan'208";a="195846094" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 09:48:54 -0700 IronPort-SDR: uOORR2PPHgVXAl/qjqZjWiHHxhmBNpuquz8LksRMaqA1TTUnHH8rCV+TnzLBY7ISZgguxQsDNM Ga+c0jDKsCHg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,240,1613462400"; d="scan'208";a="423611299" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 21 Apr 2021 09:48:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 21 Apr 2021 19:48:52 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Apr 2021 19:48:33 +0300 Message-Id: <20210421164849.12806-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210421164849.12806-1-ville.syrjala@linux.intel.com> References: <20210421164849.12806-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Give the hsw/bdw/skl buf trans stuff a better namespace. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 39 +++++---- drivers/gpu/drm/i915/display/intel_ddi.h | 4 +- .../drm/i915/display/intel_ddi_buf_trans.c | 79 +++++++++---------- .../drm/i915/display/intel_ddi_buf_trans.h | 20 +++-- drivers/gpu/drm/i915/display/intel_fdi.c | 4 +- 5 files changed, 70 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f4249f087fa7..f40472cfce10 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -93,24 +93,21 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder, * values in advance. This function programs the correct values for * DP/eDP/FDI use cases. */ -void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 iboost_bit = 0; int i, n_entries; enum port port = encoder->port; - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) - ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = intel_ddi_get_buf_trans_edp(encoder, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(encoder, - &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && @@ -130,16 +127,16 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, * values in advance. This function programs the correct values for * HDMI/DVI use cases. */ -static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, - int level) +static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, + int level) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 iboost_bit = 0; int n_entries; enum port port = encoder->port; - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; - ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -912,15 +909,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); if (iboost == 0) { - const struct ddi_buf_trans *ddi_translations; + const struct hsw_ddi_buf_trans *ddi_translations; int n_entries; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = intel_ddi_get_buf_trans_edp(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(encoder, &n_entries); + ddi_translations = hsw_ddi_get_buf_trans_dp(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -993,9 +990,9 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, bxt_get_buf_trans(encoder, crtc_state, &n_entries); } else { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - intel_ddi_get_buf_trans_edp(encoder, &n_entries); + hsw_ddi_get_buf_trans_edp(encoder, &n_entries); else - intel_ddi_get_buf_trans_dp(encoder, &n_entries); + hsw_ddi_get_buf_trans_dp(encoder, &n_entries); } if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) @@ -2653,7 +2650,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else - intel_prepare_dp_ddi_buffers(encoder, crtc_state); + hsw_prepare_dp_ddi_buffers(encoder, crtc_state); intel_ddi_power_up_lanes(encoder, crtc_state); @@ -3101,7 +3098,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_ddi_vswing_sequence(encoder, crtc_state, level); else - intel_prepare_hdmi_ddi_buffers(encoder, level); + hsw_prepare_hdmi_ddi_buffers(encoder, level); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) skl_ddi_set_iboost(encoder, crtc_state, level); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 59c6b01d4199..7d448485d887 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -40,8 +40,8 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder); void hsw_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); -void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port); void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 58d6417b8f3e..5b8c67c439a7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -12,7 +12,7 @@ * them for both DP and FDI transports, allowing those ports to * automatically adapt to HDMI connections as well */ -static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_dp[] = { { 0x00FFFFFF, 0x0006000E, 0x0 }, { 0x00D75FFF, 0x0005000A, 0x0 }, { 0x00C30FFF, 0x00040006, 0x0 }, @@ -24,7 +24,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { { 0x80D75FFF, 0x000B0000, 0x0 }, }; -static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_fdi[] = { { 0x00FFFFFF, 0x0007000E, 0x0 }, { 0x00D75FFF, 0x000F000A, 0x0 }, { 0x00C30FFF, 0x00060006, 0x0 }, @@ -36,7 +36,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { { 0x00D75FFF, 0x001E0000, 0x0 }, }; -static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans hsw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV d db */ { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ @@ -52,7 +52,7 @@ static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ }; -static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_edp[] = { { 0x00FFFFFF, 0x00000012, 0x0 }, { 0x00EBAFFF, 0x00020011, 0x0 }, { 0x00C71FFF, 0x0006000F, 0x0 }, @@ -64,7 +64,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { { 0x00DB6FFF, 0x000A000C, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_dp[] = { { 0x00FFFFFF, 0x0007000E, 0x0 }, { 0x00D75FFF, 0x000E000A, 0x0 }, { 0x00BEFFFF, 0x00140006, 0x0 }, @@ -76,7 +76,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { { 0x80D75FFF, 0x001B0002, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_fdi[] = { { 0x00FFFFFF, 0x0001000E, 0x0 }, { 0x00D75FFF, 0x0004000A, 0x0 }, { 0x00C30FFF, 0x00070006, 0x0 }, @@ -88,7 +88,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { { 0x00D75FFF, 0x000C0000, 0x0 }, }; -static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans bdw_ddi_translations_hdmi[] = { /* Idx NT mV d T mV df db */ { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ @@ -103,7 +103,7 @@ static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { }; /* Skylake H and S */ -static const struct ddi_buf_trans skl_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_dp[] = { { 0x00002016, 0x000000A0, 0x0 }, { 0x00005012, 0x0000009B, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -116,7 +116,7 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = { }; /* Skylake U */ -static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_u_ddi_translations_dp[] = { { 0x0000201B, 0x000000A2, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x1 }, @@ -129,7 +129,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { }; /* Skylake Y */ -static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_dp[] = { { 0x00000018, 0x000000A2, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -142,7 +142,7 @@ static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { }; /* Kabylake H and S */ -static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_ddi_translations_dp[] = { { 0x00002016, 0x000000A0, 0x0 }, { 0x00005012, 0x0000009B, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -155,7 +155,7 @@ static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { }; /* Kabylake U */ -static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_u_ddi_translations_dp[] = { { 0x0000201B, 0x000000A1, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -168,7 +168,7 @@ static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { }; /* Kabylake Y */ -static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { +static const struct hsw_ddi_buf_trans kbl_y_ddi_translations_dp[] = { { 0x00001017, 0x000000A1, 0x0 }, { 0x00005012, 0x00000088, 0x0 }, { 0x80007011, 0x000000CD, 0x3 }, @@ -184,7 +184,7 @@ static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { * Skylake/Kabylake H and S * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000A9, 0x0 }, { 0x00007011, 0x000000A2, 0x0 }, @@ -201,7 +201,7 @@ static const struct ddi_buf_trans skl_ddi_translations_edp[] = { * Skylake/Kabylake U * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_u_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000A9, 0x0 }, { 0x00007011, 0x000000A2, 0x0 }, @@ -218,7 +218,7 @@ static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { * Skylake/Kabylake Y * eDP 1.4 low vswing translation parameters */ -static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_edp[] = { { 0x00000018, 0x000000A8, 0x0 }, { 0x00004013, 0x000000AB, 0x0 }, { 0x00007011, 0x000000A4, 0x0 }, @@ -232,7 +232,7 @@ static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { }; /* Skylake/Kabylake U, H and S */ -static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans skl_ddi_translations_hdmi[] = { { 0x00000018, 0x000000AC, 0x0 }, { 0x00005012, 0x0000009D, 0x0 }, { 0x00007011, 0x00000088, 0x0 }, @@ -247,7 +247,7 @@ static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { }; /* Skylake/Kabylake Y */ -static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { +static const struct hsw_ddi_buf_trans skl_y_ddi_translations_hdmi[] = { { 0x00000018, 0x000000A1, 0x0 }, { 0x00005012, 0x000000DF, 0x0 }, { 0x80007011, 0x000000CB, 0x3 }, @@ -261,7 +261,6 @@ static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { { 0x80000018, 0x000000C0, 0x3 }, }; - static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { /* Idx NT mV diff db */ { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ @@ -739,7 +738,7 @@ bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -753,7 +752,7 @@ bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -770,7 +769,7 @@ skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -791,7 +790,7 @@ kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) } } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -823,7 +822,7 @@ skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return skl_get_buf_trans_dp(encoder, n_entries); } -static const struct ddi_buf_trans * +static const struct hsw_ddi_buf_trans * skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { if (IS_SKL_ULX(dev_priv) || @@ -847,20 +846,20 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) return min(n_entries, 9); } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = kbl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; } else if (IS_SKYLAKE(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = skl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -876,13 +875,13 @@ intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { - const struct ddi_buf_trans *ddi_translations = + const struct hsw_ddi_buf_trans *ddi_translations = skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); return ddi_translations; @@ -897,9 +896,9 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, - int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, + int *n_entries) { if (IS_BROADWELL(dev_priv)) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); @@ -913,9 +912,9 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, return NULL; } -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries) +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, + int *n_entries) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -1374,13 +1373,13 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, bxt_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = n_entries - 1; } else if (DISPLAY_VER(dev_priv) == 9) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 7; } else if (IS_HASWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); + hsw_ddi_get_buf_trans_hdmi(encoder, &n_entries); *default_entry = 6; } else { drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index f8f0ef87e977..6147d089e8e4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -12,7 +12,7 @@ struct drm_i915_private; struct intel_encoder; struct intel_crtc_state; -struct ddi_buf_trans { +struct hsw_ddi_buf_trans { u32 trans1; /* balance leg enable, de-emph level */ u32 trans2; /* vref sel, vswing */ u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ @@ -51,16 +51,14 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *default_entry); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, - int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, - int *n_entries); -const struct ddi_buf_trans * -intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries); +const struct hsw_ddi_buf_trans * +hsw_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries); const struct bxt_ddi_buf_trans * bxt_get_buf_trans(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index d719cd9c5b73..4ee7dd2e124f 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -568,9 +568,9 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, u32 temp, i, rx_ctl_val; int n_entries; - intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries); + hsw_ddi_get_buf_trans_fdi(dev_priv, &n_entries); - intel_prepare_dp_ddi_buffers(encoder, crtc_state); + hsw_prepare_dp_ddi_buffers(encoder, crtc_state); /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the * mode set "sequence for CRT port" document: