From patchwork Thu Apr 22 18:29:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 12219039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C853C433B4 for ; Thu, 22 Apr 2021 18:30:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1C5A61405 for ; Thu, 22 Apr 2021 18:30:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E1C5A61405 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 536066E57A; Thu, 22 Apr 2021 18:30:05 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8CA216E57A for ; Thu, 22 Apr 2021 18:30:04 +0000 (UTC) IronPort-SDR: TQOL05Mu4/K4uzxf+qT/DlJfiEFxKHrgC8d7Spj0oUJ1DM13V/cu5p9r0PpBc2OJFoSBhoK7xJ 95IlSehKBNKw== X-IronPort-AV: E=McAfee;i="6200,9189,9962"; a="193829958" X-IronPort-AV: E=Sophos;i="5.82,243,1613462400"; d="scan'208";a="193829958" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2021 11:30:03 -0700 IronPort-SDR: sPjYb1MiCdy/UwanwEC+8sRfhg8gFo8+m2uYsVQekO8UlyKVehMQ5DBPXLpe2UpdCfLzhOmD7t jBx9vG+Ehs0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,243,1613462400"; d="scan'208";a="421471877" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 22 Apr 2021 11:30:01 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 22 Apr 2021 21:30:00 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Apr 2021 21:29:56 +0300 Message-Id: <20210422182957.10022-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210422182957.10022-1-ville.syrjala@linux.intel.com> References: <20210422182957.10022-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/fbc: Don't nuke manually around flips X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Apparently we have discovered another way to hit the dreaded top of screen FBC corruption on GLK. Previously we thought it was limited to some combination of FBC nuke+disable+plane update during the same frame, for which we have the extra vblank wait as a workaround. But looks like it can be hit even if the plane update happens during a different frame. Skipping the extra manual nuke immediately after page flips seems to cure this. The manual nuke shouldn't be needed anyway since the flip itself will already cause a nuke. I suppose this means it might still be possible to hit this if you mix page flips and frontbuffer rendering in clever ways, but at least it's a bit less likely now. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 91dad8004c34..4fc3633eb614 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -232,7 +232,8 @@ static void intel_fbc_recompress(struct drm_i915_private *dev_priv) static void ilk_fbc_activate(struct drm_i915_private *dev_priv) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc_reg_params *params = &fbc->params; u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; @@ -275,7 +276,8 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) /* enable it... */ intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); - intel_fbc_recompress(dev_priv); + if (!fbc->active) + intel_fbc_recompress(dev_priv); } static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -297,7 +299,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) static void gen7_fbc_activate(struct drm_i915_private *dev_priv) { - struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc_reg_params *params = &fbc->params; u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; @@ -349,7 +352,8 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); - intel_fbc_recompress(dev_priv); + if (!fbc->active) + intel_fbc_recompress(dev_priv); } static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) @@ -368,9 +372,6 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) trace_intel_fbc_activate(fbc->crtc); - fbc->active = true; - fbc->activated = true; - if (DISPLAY_VER(dev_priv) >= 7) gen7_fbc_activate(dev_priv); else if (DISPLAY_VER(dev_priv) >= 5) @@ -379,6 +380,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) g4x_fbc_activate(dev_priv); else i8xx_fbc_activate(dev_priv); + + fbc->active = true; + fbc->activated = true; } static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)