diff mbox series

[v3,01/48] drm/i915/xelpd: Handle proper AUX interrupt bits

Message ID 20210508022820.780227-2-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series Alder Lake-P Support | expand

Commit Message

Matt Roper May 8, 2021, 2:27 a.m. UTC
XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
spots that were used by TC5/TC6 on Display12 platforms.

While we're at it, let's convert the bit definitions for all TGL+ aux
bits over to the modern REG_BIT() notation.

v2:
 - Maintain bit order rather than logical order.  (Lucas)
 - Convert surrounding code to REG_BIT() notation.  (Lucas)

Bspec: 50064
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
 drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
 2 files changed, 22 insertions(+), 10 deletions(-)

Comments

Lucas De Marchi May 12, 2021, 9:37 p.m. UTC | #1
On Fri, May 07, 2021 at 07:27:33PM -0700, Matt Roper wrote:
>XE_LPD has new AUX interrupt bits for DDI-D and DDI-E that take the
>spots that were used by TC5/TC6 on Display12 platforms.
>
>While we're at it, let's convert the bit definitions for all TGL+ aux
>bits over to the modern REG_BIT() notation.
>
>v2:
> - Maintain bit order rather than logical order.  (Lucas)
> - Convert surrounding code to REG_BIT() notation.  (Lucas)
>
>Bspec: 50064
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 12 +++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++++---------
> 2 files changed, 22 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index f6967a93ec7a..26a5474bb145 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2270,7 +2270,17 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
> {
> 	u32 mask;
>
>-	if (DISPLAY_VER(dev_priv) >= 12)
>+	if (DISPLAY_VER(dev_priv) >= 13)
>+		return TGL_DE_PORT_AUX_DDIA |
>+			TGL_DE_PORT_AUX_DDIB |
>+			TGL_DE_PORT_AUX_DDIC |
>+			XELPD_DE_PORT_AUX_DDID |
>+			XELPD_DE_PORT_AUX_DDIE |
>+			TGL_DE_PORT_AUX_USBC1 |
>+			TGL_DE_PORT_AUX_USBC2 |
>+			TGL_DE_PORT_AUX_USBC3 |
>+			TGL_DE_PORT_AUX_USBC4;
>+	else if (DISPLAY_VER(dev_priv) >= 12)
> 		return TGL_DE_PORT_AUX_DDIA |
> 			TGL_DE_PORT_AUX_DDIB |
> 			TGL_DE_PORT_AUX_DDIC |
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 846fa927a3d8..87d7257922d0 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7873,15 +7873,17 @@ enum {
> #define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
> #define  BXT_DE_PORT_GMBUS		(1 << 1)
> #define  GEN8_AUX_CHANNEL_A		(1 << 0)
>-#define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
>-#define  TGL_DE_PORT_AUX_USBC5		(1 << 12)
>-#define  TGL_DE_PORT_AUX_USBC4		(1 << 11)
>-#define  TGL_DE_PORT_AUX_USBC3		(1 << 10)
>-#define  TGL_DE_PORT_AUX_USBC2		(1 << 9)
>-#define  TGL_DE_PORT_AUX_USBC1		(1 << 8)
>-#define  TGL_DE_PORT_AUX_DDIC		(1 << 2)
>-#define  TGL_DE_PORT_AUX_DDIB		(1 << 1)
>-#define  TGL_DE_PORT_AUX_DDIA		(1 << 0)
>+#define  TGL_DE_PORT_AUX_USBC6		REG_BIT(13)
>+#define  XELPD_DE_PORT_AUX_DDIE		REG_BIT(13)
>+#define  TGL_DE_PORT_AUX_USBC5		REG_BIT(12)
>+#define  XELPD_DE_PORT_AUX_DDID		REG_BIT(12)
>+#define  TGL_DE_PORT_AUX_USBC4		REG_BIT(11)
>+#define  TGL_DE_PORT_AUX_USBC3		REG_BIT(10)
>+#define  TGL_DE_PORT_AUX_USBC2		REG_BIT(9)
>+#define  TGL_DE_PORT_AUX_USBC1		REG_BIT(8)
>+#define  TGL_DE_PORT_AUX_DDIC		REG_BIT(2)
>+#define  TGL_DE_PORT_AUX_DDIB		REG_BIT(1)
>+#define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
>
> #define GEN8_DE_MISC_ISR _MMIO(0x44460)
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>-- 
>2.25.4
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f6967a93ec7a..26a5474bb145 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2270,7 +2270,17 @@  static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
 {
 	u32 mask;
 
-	if (DISPLAY_VER(dev_priv) >= 12)
+	if (DISPLAY_VER(dev_priv) >= 13)
+		return TGL_DE_PORT_AUX_DDIA |
+			TGL_DE_PORT_AUX_DDIB |
+			TGL_DE_PORT_AUX_DDIC |
+			XELPD_DE_PORT_AUX_DDID |
+			XELPD_DE_PORT_AUX_DDIE |
+			TGL_DE_PORT_AUX_USBC1 |
+			TGL_DE_PORT_AUX_USBC2 |
+			TGL_DE_PORT_AUX_USBC3 |
+			TGL_DE_PORT_AUX_USBC4;
+	else if (DISPLAY_VER(dev_priv) >= 12)
 		return TGL_DE_PORT_AUX_DDIA |
 			TGL_DE_PORT_AUX_DDIB |
 			TGL_DE_PORT_AUX_DDIC |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 846fa927a3d8..87d7257922d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7873,15 +7873,17 @@  enum {
 #define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
-#define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
-#define  TGL_DE_PORT_AUX_USBC5		(1 << 12)
-#define  TGL_DE_PORT_AUX_USBC4		(1 << 11)
-#define  TGL_DE_PORT_AUX_USBC3		(1 << 10)
-#define  TGL_DE_PORT_AUX_USBC2		(1 << 9)
-#define  TGL_DE_PORT_AUX_USBC1		(1 << 8)
-#define  TGL_DE_PORT_AUX_DDIC		(1 << 2)
-#define  TGL_DE_PORT_AUX_DDIB		(1 << 1)
-#define  TGL_DE_PORT_AUX_DDIA		(1 << 0)
+#define  TGL_DE_PORT_AUX_USBC6		REG_BIT(13)
+#define  XELPD_DE_PORT_AUX_DDIE		REG_BIT(13)
+#define  TGL_DE_PORT_AUX_USBC5		REG_BIT(12)
+#define  XELPD_DE_PORT_AUX_DDID		REG_BIT(12)
+#define  TGL_DE_PORT_AUX_USBC4		REG_BIT(11)
+#define  TGL_DE_PORT_AUX_USBC3		REG_BIT(10)
+#define  TGL_DE_PORT_AUX_USBC2		REG_BIT(9)
+#define  TGL_DE_PORT_AUX_USBC1		REG_BIT(8)
+#define  TGL_DE_PORT_AUX_DDIC		REG_BIT(2)
+#define  TGL_DE_PORT_AUX_DDIB		REG_BIT(1)
+#define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
 
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)