From patchwork Sat May 8 02:28:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12245671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAA77C43460 for ; Sat, 8 May 2021 02:29:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 860FB610A2 for ; Sat, 8 May 2021 02:29:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 860FB610A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C940C6EEB9; Sat, 8 May 2021 02:28:36 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id E65456E834 for ; Sat, 8 May 2021 02:28:31 +0000 (UTC) IronPort-SDR: NpgEcyOhhU2Xjki86Efk+h+KL5c24H6Nm+75OipoazdMZI0V/jXPgw9LMKztZWigTD0H6OuP7Y 0yKyjm5iTCvw== X-IronPort-AV: E=McAfee;i="6200,9189,9977"; a="284317023" X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="284317023" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 19:28:30 -0700 IronPort-SDR: UAYSESDGHcnqqwJZj1Cpxb4IHyFKC/ofyr3Z+xOFaTMq1jBCu//uVafoaV5gV5dAiJSz9FggZF dA3TeY5lyktw== X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="533910136" Received: from mdroper-desk1.fm.intel.com ([10.1.27.168]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 19:28:29 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Fri, 7 May 2021 19:28:05 -0700 Message-Id: <20210508022820.780227-34-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210508022820.780227-1-matthew.d.roper@intel.com> References: <20210508022820.780227-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 33/48] drm/i915/display: Add PSR interrupt error check function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Gwan-gyeong Mun In order to reuse code of PSR interrupt error check on other PSR functions, it adds psr_interrupt_error_check() function. Cc: José Roberto de Souza Signed-off-by: Gwan-gyeong Mun Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_psr.c | 47 +++++++++++++++--------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 77a78982b174..599c6b1089e5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -984,27 +984,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) IGNORE_PSR2_HW_TRACKING : 0); } -static void intel_psr_enable_locked(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) +static bool psr_interrupt_error_check(struct intel_dp *intel_dp) { - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_encoder *encoder = &dig_port->base; u32 val; - drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; - intel_dp->psr.busy_frontbuffer_bits = 0; - intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; - intel_dp->psr.transcoder = crtc_state->cpu_transcoder; - /* DC5/DC6 requires at least 6 idle frames */ - val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); - intel_dp->psr.dc3co_exit_delay = val; - intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; - intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; - /* * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR * will still keep the error set even after the reset done in the @@ -1025,9 +1009,36 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.sink_not_reliable = true; drm_dbg_kms(&dev_priv->drm, "PSR interruption error set, not enabling PSR\n"); - return; + return false; } + return true; +} + +static void intel_psr_enable_locked(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_encoder *encoder = &dig_port->base; + u32 val; + + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); + + intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.busy_frontbuffer_bits = 0; + intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; + intel_dp->psr.transcoder = crtc_state->cpu_transcoder; + /* DC5/DC6 requires at least 6 idle frames */ + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); + intel_dp->psr.dc3co_exit_delay = val; + intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; + intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; + + if (!psr_interrupt_error_check(intel_dp)) + return; + drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", intel_dp->psr.psr2_enabled ? "2" : "1"); intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,