diff mbox series

[v4,17/23] drm/i915/display: Add PSR interrupt error check function

Message ID 20210515031035.2561658-18-matthew.d.roper@intel.com (mailing list archive)
State New, archived
Headers show
Series Alder Lake-P Support | expand

Commit Message

Matt Roper May 15, 2021, 3:10 a.m. UTC
From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

In order to reuse code of PSR interrupt error check on other PSR functions,
it adds psr_interrupt_error_check() function.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 47 +++++++++++++++---------
 1 file changed, 29 insertions(+), 18 deletions(-)

Comments

Souza, Jose May 17, 2021, 5:03 p.m. UTC | #1
On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> In order to reuse code of PSR interrupt error check on other PSR functions,
> it adds psr_interrupt_error_check() function.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 47 +++++++++++++++---------
>  1 file changed, 29 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cc85083dcd28..4a63d10876ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1029,27 +1029,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>  			     IGNORE_PSR2_HW_TRACKING : 0);
>  }
>  
> -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> -				    const struct intel_crtc_state *crtc_state,
> -				    const struct drm_connector_state *conn_state)
> +static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
>  {
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct intel_encoder *encoder = &dig_port->base;
>  	u32 val;
>  
> -	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> -
> -	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> -	intel_dp->psr.busy_frontbuffer_bits = 0;
> -	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> -	/* DC5/DC6 requires at least 6 idle frames */
> -	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> -	intel_dp->psr.dc3co_exit_delay = val;
> -	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> -	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> -
>  	/*
>  	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
>  	 * will still keep the error set even after the reset done in the
> @@ -1070,9 +1054,36 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  		intel_dp->psr.sink_not_reliable = true;
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR interruption error set, not enabling PSR\n");
> -		return;
> +		return false;
>  	}
>  
> +	return true;
> +}
> +
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	struct intel_encoder *encoder = &dig_port->base;
> +	u32 val;
> +
> +	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> +
> +	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.busy_frontbuffer_bits = 0;
> +	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> +	/* DC5/DC6 requires at least 6 idle frames */
> +	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> +	intel_dp->psr.dc3co_exit_delay = val;
> +	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> +	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> +
> +	if (!psr_interrupt_error_check(intel_dp))
> +		return;
> +
>  	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
>  		    intel_dp->psr.psr2_enabled ? "2" : "1");
>  	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cc85083dcd28..4a63d10876ce 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1029,27 +1029,11 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp)
 			     IGNORE_PSR2_HW_TRACKING : 0);
 }
 
-static void intel_psr_enable_locked(struct intel_dp *intel_dp,
-				    const struct intel_crtc_state *crtc_state,
-				    const struct drm_connector_state *conn_state)
+static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 {
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct intel_encoder *encoder = &dig_port->base;
 	u32 val;
 
-	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
-
-	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
-	intel_dp->psr.busy_frontbuffer_bits = 0;
-	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
-	/* DC5/DC6 requires at least 6 idle frames */
-	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
-	intel_dp->psr.dc3co_exit_delay = val;
-	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
-	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
-
 	/*
 	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
 	 * will still keep the error set even after the reset done in the
@@ -1070,9 +1054,36 @@  static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 		intel_dp->psr.sink_not_reliable = true;
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR interruption error set, not enabling PSR\n");
-		return;
+		return false;
 	}
 
+	return true;
+}
+
+static void intel_psr_enable_locked(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_encoder *encoder = &dig_port->base;
+	u32 val;
+
+	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
+
+	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.busy_frontbuffer_bits = 0;
+	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
+	/* DC5/DC6 requires at least 6 idle frames */
+	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
+	intel_dp->psr.dc3co_exit_delay = val;
+	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
+	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+
+	if (!psr_interrupt_error_check(intel_dp))
+		return;
+
 	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 		    intel_dp->psr.psr2_enabled ? "2" : "1");
 	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,