| Message ID | 20210515031035.2561658-23-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Alder Lake-P Support | expand |
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> -Clint On 5/14/21 8:10 PM, Matt Roper wrote: > From: Anusha Srivatsa <anusha.srivatsa@intel.com> > > When scalers are enabled, we need to program underrun > bubble counter to 0x50 to avoid Soft Pipe A underruns. > Make sure other bits dont get overwritten. > > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Clint Taylor <clinton.a.taylor@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ > 2 files changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index dd248995c53d..85077caa3744 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5716,8 +5716,12 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) > static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + const struct intel_crtc_scaler_state *scaler_state = > + &crtc_state->scaler_state; > + > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > u32 val = 0; > + int i; > > switch (crtc_state->pipe_bpp) { > case 18: > @@ -5756,6 +5760,23 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) > if (DISPLAY_VER(dev_priv) >= 12) > val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; > > + if (IS_ALDERLAKE_P(dev_priv)) { > + bool scaler_in_use = false; > + > + for (i = 0; i < crtc->num_scalers; i++) { > + if (!scaler_state->scalers[i].in_use) > + continue; > + > + scaler_in_use = true; > + break; > + } > + > + intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe), > + PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK, > + scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN : > + PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS); > + } > + > intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9b8da4a6a0ae..6fd126b64727 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6163,6 +6163,13 @@ enum { > #define PIPEMISC_DITHER_TYPE_SP (0 << 2) > #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) > > +#define _PIPE_MISC2_A 0x7002C > +#define _PIPE_MISC2_B 0x7102C > +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24) > +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24) > +#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24) > +#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) > + > /* Skylake+ pipe bottom (background) color */ > #define _SKL_BOTTOM_COLOR_A 0x70034 > #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index dd248995c53d..85077caa3744 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5716,8 +5716,12 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + const struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 val = 0; + int i; switch (crtc_state->pipe_bpp) { case 18: @@ -5756,6 +5760,23 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(dev_priv) >= 12) val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; + if (IS_ALDERLAKE_P(dev_priv)) { + bool scaler_in_use = false; + + for (i = 0; i < crtc->num_scalers; i++) { + if (!scaler_state->scalers[i].in_use) + continue; + + scaler_in_use = true; + break; + } + + intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe), + PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK, + scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN : + PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS); + } + intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9b8da4a6a0ae..6fd126b64727 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6163,6 +6163,13 @@ enum { #define PIPEMISC_DITHER_TYPE_SP (0 << 2) #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) +#define _PIPE_MISC2_A 0x7002C +#define _PIPE_MISC2_B 0x7102C +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN (0x50 << 24) +#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS (0x14 << 24) +#define PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK (0xff << 24) +#define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) + /* Skylake+ pipe bottom (background) color */ #define _SKL_BOTTOM_COLOR_A 0x70034 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)