From patchwork Mon May 24 21:48:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12277017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAFD8C04FF3 for ; Mon, 24 May 2021 21:45:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 688CE6140F for ; Mon, 24 May 2021 21:45:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 688CE6140F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB1F56E975; Mon, 24 May 2021 21:44:58 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7835E6E971 for ; Mon, 24 May 2021 21:44:57 +0000 (UTC) IronPort-SDR: r69fT5rn3wnxDkzwhlFUJiMb7j12ss5basOJUb7laldVc1bjNJc+RjIYOO8qpB++1eI8RZFE+U reTSHwtRTRPw== X-IronPort-AV: E=McAfee;i="6200,9189,9994"; a="181677508" X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="181677508" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 14:44:55 -0700 IronPort-SDR: v7g398195D+pxHTVLPoPr6PjLxoYx4gYdOlEs41H89x8yN7psDQzzVAqthQbBikixoLY1MWIRC F1O86Cpj4O7A== X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="546513298" Received: from xxi2-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.32.238]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 14:44:55 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 24 May 2021 14:48:03 -0700 Message-Id: <20210524214805.259692-3-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210524214805.259692-1-jose.souza@intel.com> References: <20210524214805.259692-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Commit c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL") assumes that we always have a non-zero dram_info->channels and uses it as a divisor. We need num memory channels to be at least 1 for sane bw limits checking, even when PCode returns 0 or there is a error reading it, so lets force it to 1 in this case. Cc: Stanislav Lisovskiy Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi Signed-off-by: José Roberto de Souza Reviewed-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_bw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 3a1ba52266a7..bfb398f0432e 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -162,7 +162,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel { struct intel_qgv_info qi = {}; bool is_y_tile = true; /* assume y tile may be used */ - int num_channels = dev_priv->dram_info.num_channels; + int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); int deinterleave; int ipqdepth, ipqdepthpch; int dclk_max;