From patchwork Mon May 24 21:48:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 12277019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84720C2B9F7 for ; Mon, 24 May 2021 21:45:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A89D613F5 for ; Mon, 24 May 2021 21:45:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4A89D613F5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 123486E976; Mon, 24 May 2021 21:44:59 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 787616E972 for ; Mon, 24 May 2021 21:44:57 +0000 (UTC) IronPort-SDR: QuzBElxN+Y0vgDg+xoc9Tg1q5ohIXBGo803uUH7KLV8bulbbGgwDFb95icci6xawrwHVoOedZz ror1dtz1Xv4Q== X-IronPort-AV: E=McAfee;i="6200,9189,9994"; a="181677510" X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="181677510" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 14:44:56 -0700 IronPort-SDR: IBpNOhHYO/ObhPklyztUxNS3Kq3Z5+x00YEhus+c5eFC9tT1LMWyxUcHXmbq9zYe2ZTfyxCFa3 aJK6rkdCflRA== X-IronPort-AV: E=Sophos;i="5.82,325,1613462400"; d="scan'208";a="546513301" Received: from xxi2-mobl.amr.corp.intel.com (HELO josouza-mobl2.intel.com) ([10.254.32.238]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 14:44:55 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Mon, 24 May 2021 14:48:04 -0700 Message-Id: <20210524214805.259692-4-jose.souza@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210524214805.259692-1-jose.souza@intel.com> References: <20210524214805.259692-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/5] drm/i915/display/adl_p: Allow DC3CO in pipe and port B X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DC3CO is allowed in all the combinations between pipe and port A and B on alderlake-P. BSpec: 49196 Cc: Anshuman Gupta Cc: Gwan-gyeong Mun Cc: Matt Atwood Signed-off-by: José Roberto de Souza Reviewed-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 216626444c76..c57210862206 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -646,12 +646,26 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) tgl_psr2_disable_dc3co(intel_dp); } +static bool +dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + enum port port = dig_port->base.port; + + if (IS_ALDERLAKE_P(dev_priv)) + return pipe <= PIPE_B && port <= PORT_B; + else + return pipe == PIPE_A && port == PORT_A; +} + static void tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 exit_scanlines; @@ -672,9 +686,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO)) return; - /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ - if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || - dig_port->base.port != PORT_A) + if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) return; /*