| Message ID | 20210526173600.27708-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/adl_p: Disable FIFO underrun recovery | expand |
On Wed, 2021-05-26 at 20:35 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The FIFO underrun recovery mechanism has a boatload of cases > where it can't be used. The description is also a bit ambiguous > as it doesn't specify whether plane downscaling needs to be considered > or just pipe downscaling. We may not even have sufficient state > tracking to decide this on demand, so for now just disable the > whole thing. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index d1ee95512282..a2f3d255a906 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2208,6 +2208,21 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) > * across pipe > */ > tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; > + > + /* > + * "The underrun recovery mechanism should be disabled > + * when the following is enabled for this pipe: > + * WiDi > + * Downscaling (this includes YUV420 fullblend) > + * COG > + * DSC > + * PSR2" > + * > + * FIXME: enable whenever possible... > + */ > + if (IS_ALDERLAKE_P(dev_priv)) > + tmp |= UNDERRUN_RECOVERY_DISABLE; > + > intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4979b4965a82..e4d6336dab71 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8368,6 +8368,7 @@ enum { > #define _PIPEC_CHICKEN 0x72038 > #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ > _PIPEB_CHICKEN) > +#define UNDERRUN_RECOVERY_DISABLE REG_BIT(30) > #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) > #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d1ee95512282..a2f3d255a906 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2208,6 +2208,21 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) * across pipe */ tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; + + /* + * "The underrun recovery mechanism should be disabled + * when the following is enabled for this pipe: + * WiDi + * Downscaling (this includes YUV420 fullblend) + * COG + * DSC + * PSR2" + * + * FIXME: enable whenever possible... + */ + if (IS_ALDERLAKE_P(dev_priv)) + tmp |= UNDERRUN_RECOVERY_DISABLE; + intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4979b4965a82..e4d6336dab71 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8368,6 +8368,7 @@ enum { #define _PIPEC_CHICKEN 0x72038 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ _PIPEB_CHICKEN) +#define UNDERRUN_RECOVERY_DISABLE REG_BIT(30) #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)