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[8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config

Message ID 20210601104135.29020-9-uma.shankar@intel.com (mailing list archive)
State New, archived
Headers show
Series Enhance pipe color support for multi segmented luts | expand

Commit Message

Shankar, Uma June 1, 2021, 10:41 a.m. UTC
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..844d08e37ec5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -947,7 +947,8 @@  static const struct intel_device_info adl_s_info = {
 	.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |	\
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),			\
 	.dbuf.size = 4096,						\
-	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
+	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), \
+	.color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }
 
 static const struct intel_device_info adl_p_info = {
 	GEN12_FEATURES,