From patchwork Tue Jun 8 07:35:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12305545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4785C48BCD for ; Tue, 8 Jun 2021 07:36:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7256C610C7 for ; Tue, 8 Jun 2021 07:36:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7256C610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1ADF36EADC; Tue, 8 Jun 2021 07:36:36 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FBFB6EAF0 for ; Tue, 8 Jun 2021 07:36:34 +0000 (UTC) IronPort-SDR: OfWtHoaOoZDrZUnD1g0xUTpo78VVE2yBlQYF7pqH+RMDPs5ozOYOK7DFWMiXD+dQ8f29s1muJ8 /cAEp3Sip2fg== X-IronPort-AV: E=McAfee;i="6200,9189,10008"; a="204605195" X-IronPort-AV: E=Sophos;i="5.83,257,1616482800"; d="scan'208";a="204605195" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2021 00:36:34 -0700 IronPort-SDR: +ka5uDe5d4+PvAMHEZoa9q1LcQ3yNsdg1Xsswsmm2AoBtWgSMaM6BD5FzpAwYArTuSngr+/qTv 27XcaHuHSjDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,257,1616482800"; d="scan'208";a="401891680" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 08 Jun 2021 00:36:31 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 08 Jun 2021 10:36:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Jun 2021 10:35:54 +0300 Message-Id: <20210608073603.2408-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210608073603.2408-1-ville.syrjala@linux.intel.com> References: <20210608073603.2408-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 08/17] drm/i915: Store the HDMI default entry in the bug trans struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Store the default HDMI buf trans entry in struct intel_ddi_buf_trans so that it's next to the actual table. This let's us start ridding ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries(). Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_ddi_buf_trans.c | 49 ++++++++++--------- .../drm/i915/display/intel_ddi_buf_trans.h | 1 + 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 95b8f9b43ea2..fd2216dc8c33 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -66,6 +66,7 @@ static const union intel_ddi_buf_trans_entry _hsw_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans hsw_ddi_translations_hdmi = { .entries = _hsw_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_hsw_ddi_translations_hdmi), + .hdmi_default_entry = 6, }; static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_edp[] = { @@ -136,6 +137,7 @@ static const union intel_ddi_buf_trans_entry _bdw_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans bdw_ddi_translations_hdmi = { .entries = _bdw_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_bdw_ddi_translations_hdmi), + .hdmi_default_entry = 7, }; /* Skylake H and S */ @@ -330,6 +332,7 @@ static const union intel_ddi_buf_trans_entry _skl_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans skl_ddi_translations_hdmi = { .entries = _skl_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_skl_ddi_translations_hdmi), + .hdmi_default_entry = 8, }; /* Skylake/Kabylake Y */ @@ -350,6 +353,7 @@ static const union intel_ddi_buf_trans_entry _skl_y_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans skl_y_ddi_translations_hdmi = { .entries = _skl_y_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_skl_y_ddi_translations_hdmi), + .hdmi_default_entry = 8, }; static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_dp[] = { @@ -410,6 +414,7 @@ static const union intel_ddi_buf_trans_entry _bxt_ddi_translations_hdmi[] = { static const struct intel_ddi_buf_trans bxt_ddi_translations_hdmi = { .entries = _bxt_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_bxt_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_bxt_ddi_translations_hdmi) - 1, }; /* Voltage Swing Programming for VccIO 0.85V for DP */ @@ -447,6 +452,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_85V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V = { .entries = _cnl_ddi_translations_hdmi_0_85V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_85V) - 1, }; /* Voltage Swing Programming for VccIO 0.85V for eDP */ @@ -507,6 +513,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_0_95V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V = { .entries = _cnl_ddi_translations_hdmi_0_95V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_0_95V) - 1, }; /* Voltage Swing Programming for VccIO 0.95V for eDP */ @@ -568,6 +575,7 @@ static const union intel_ddi_buf_trans_entry _cnl_ddi_translations_hdmi_1_05V[] static const struct intel_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V = { .entries = _cnl_ddi_translations_hdmi_1_05V, .num_entries = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V), + .hdmi_default_entry = ARRAY_SIZE(_cnl_ddi_translations_hdmi_1_05V) - 1, }; /* Voltage Swing Programming for VccIO 1.05V for eDP */ @@ -661,6 +669,7 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdm static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi = { .entries = _icl_combo_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _ehl_combo_phy_ddi_translations_dp[] = { @@ -813,6 +822,7 @@ static const union intel_ddi_buf_trans_entry _icl_mg_phy_ddi_translations_hdmi[] static const struct intel_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi = { .entries = _icl_mg_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_dp_hbr[] = { @@ -870,6 +880,7 @@ static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_ddi_translations_hdmi[ static const struct intel_ddi_buf_trans tgl_dkl_phy_ddi_translations_hdmi = { .entries = _tgl_dkl_phy_ddi_translations_hdmi, .num_entries = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi), + .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_ddi_translations_hdmi) - 1, }; static const union intel_ddi_buf_trans_entry _tgl_combo_phy_ddi_translations_dp_hbr[] = { @@ -1693,42 +1704,34 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum phy phy = intel_port_to_phy(dev_priv, encoder->port); + const struct intel_ddi_buf_trans *ddi_translations = NULL; int n_entries; if (DISPLAY_VER(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); + ddi_translations = tgl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); else - tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, &n_entries); } else if (DISPLAY_VER(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); + ddi_translations = icl_get_combo_buf_trans_hdmi(encoder, crtc_state, &n_entries); else - icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = icl_get_mg_buf_trans_hdmi(encoder, crtc_state, &n_entries); } else if (IS_CANNONLAKE(dev_priv)) { - cnl_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = n_entries - 1; + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - bxt_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = n_entries - 1; - } else if (DISPLAY_VER(dev_priv) == 9) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 8; - } else if (IS_BROADWELL(dev_priv)) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 7; - } else if (IS_HASWELL(dev_priv)) { - hsw_get_buf_trans_hdmi(encoder, &n_entries); - *default_entry = 6; - } else { - drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); - return 0; + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); + } else if (DISPLAY_VER(dev_priv) == 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + ddi_translations = hsw_get_buf_trans_hdmi(encoder, &n_entries); } - if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) + if (drm_WARN_ON(&dev_priv->drm, !ddi_translations)) { + *default_entry = 0; return 0; + } + + *default_entry = ddi_translations->hdmi_default_entry; return n_entries; } diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 2ffa534010b3..879f1deec3c8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -56,6 +56,7 @@ union intel_ddi_buf_trans_entry { struct intel_ddi_buf_trans { const union intel_ddi_buf_trans_entry *entries; u8 num_entries; + u8 hdmi_default_entry; }; bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table);