From patchwork Thu Jun 17 21:12:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12329543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B48D2C49361 for ; Thu, 17 Jun 2021 21:12:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 81D3F613BF for ; Thu, 17 Jun 2021 21:12:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 81D3F613BF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 019CF6E952; Thu, 17 Jun 2021 21:12:35 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B4976E9B4 for ; Thu, 17 Jun 2021 21:12:27 +0000 (UTC) IronPort-SDR: mWA3kQ7m70T67ea6jleHGDuhC2HWj8aFG0r+Y4Zhs6yy3JdEywOQrn8b1p2KOw0PK48c370a/M P9qCkV3B7Xzg== X-IronPort-AV: E=McAfee;i="6200,9189,10018"; a="292081541" X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="292081541" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 14:12:27 -0700 IronPort-SDR: SyZbPEo62SE9JIyxiYLST4cqfe1hds/dnj0KjAHntwWPKZkdapeu2odBMFxEcMTTRc8+MVbHcr S/h4mqH9rLpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,281,1616482800"; d="scan'208";a="622168079" Received: from anushasr-mobl6.jf.intel.com ([10.165.21.155]) by orsmga005.jf.intel.com with ESMTP; 17 Jun 2021 14:12:25 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 17 Jun 2021 14:12:21 -0700 Message-Id: <20210617211225.13549-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210617211225.13549-1-anusha.srivatsa@intel.com> References: <20210617211225.13549-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR around cdclk changes to ADL-P X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Gwan-gyeong Mun Only ADL-P platform requires a temporal disabling of PSR for changing the CDCLK PLL frequency with crawling. Changing the CDCLK PLL frequency on prior platforms of ADL-P or changing the CDCLK PLL frequency without crawling on ADL-P don't need to disable of PSR. Bspec: 49207 Cc: Ville Syrjälä Cc: Mika Kahola Cc: Stanislav Lisovskiy Cc: Anusha Srivatsa Fixes: 17c1a4b7ac6f ("drm/i915: Disable PSR around cdclk change") Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_cdclk.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 613ffcc68eba..6da426d26aac 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1962,10 +1962,18 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + /* + * Only ADL-P platform requires a temporal disabling of PSR for changing + * the CDCLK PLL frequency with crawling. + * Changing the CDCLK PLL frequency on prior platforms of ADL-P or changing + * the CDCLK PLL frequency without crawling on ADL-P don't need to disable of PSR. + */ + if (IS_ALDERLAKE_P(dev_priv)) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_psr_pause(intel_dp); + intel_psr_pause(intel_dp); + } } /* @@ -1990,10 +1998,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, } mutex_unlock(&dev_priv->gmbus_mutex); - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + if (IS_ALDERLAKE_P(dev_priv)) { + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_psr_resume(intel_dp); + intel_psr_resume(intel_dp); + } } if (drm_WARN(&dev_priv->drm,