| Message ID | 20210701202427.1547543-5-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Begin enabling Xe_HP SDV and DG2 platforms | expand |
On Thu, Jul 01, 2021 at 01:23:38PM -0700, Matt Roper wrote: >From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > >On Xe_HP the fusing register is renamed and changed to have the "enable" >semantics, but otherwise remains compatible (mmio address, bitmask >ranges) with older platforms. > >To simplify things we do not add a new register definition but just stop >inverting the fusing masks before processing them. > >Bspec: 33288 This is now: Bspec: 52615 >Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >Signed-off-by: Matt Roper <matthew.d.roper@intel.com> this change above, Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi >--- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >index 88694822716a..151870d8fdd3 100644 >--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >@@ -468,7 +468,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) > if (GRAPHICS_VER(i915) < 11) > return info->engine_mask; > >- media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); >+ /* >+ * On newer platforms the fusing register is called 'enable' and has >+ * enable semantics, while on older platforms it is called 'disable' >+ * and bits have disable semantices. >+ */ >+ media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); >+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) >+ media_fuse = ~media_fuse; > > vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; > vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> >-- >2.25.4 >
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 88694822716a..151870d8fdd3 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -468,7 +468,14 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) if (GRAPHICS_VER(i915) < 11) return info->engine_mask; - media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); + /* + * On newer platforms the fusing register is called 'enable' and has + * enable semantics, while on older platforms it is called 'disable' + * and bits have disable semantices. + */ + media_fuse = intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE); + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + media_fuse = ~media_fuse; vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>