[05/13] drm/i915: Clean dpll calling convention

Message ID	20210715093530.31711-6-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=YxzO=MH=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9AC62613A9 From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Jul 2021 12:35:22 +0300 Message-Id: <20210715093530.31711-6-ville.syrjala@linux.intel.com> In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com> References: <20210715093530.31711-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/13] drm/i915: Clean dpll calling convention Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: Clean up DPLL stuff \| expand [00/13] drm/i915: Clean up DPLL stuff [01/13] drm/i915: Set output_types to EDP for vlv/chv DPLL forcing [02/13] drm/i915: Clean up gen2 DPLL readout [03/13] drm/i915: Extract ilk_update_pll_dividers() [04/13] drm/i915: Constify struct dpll all over [05/13] drm/i915: Clean dpll calling convention [06/13] drm/i915: Clean up variable names in old dpll functions [07/13] drm/i915: Remove the 'reg' local variable [08/13] drm/i915: Program DPLL P1 dividers consistently [09/13] drm/i915: Call {vlv, chv}_prepare_pll() from {vlv, chv}_enable_pll() [10/13] drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as well [11/13] drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll() [12/13] drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable() [13/13] drm/i915: Nuke intel_prepare_shared_dpll()

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 8a4c3a5e5462..907c3ca319aa 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3935,11 +3935,11 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_pll_enable(state, crtc); if (IS_CHERRYVIEW(dev_priv)) { - chv_prepare_pll(crtc, new_crtc_state); - chv_enable_pll(crtc, new_crtc_state); + chv_prepare_pll(new_crtc_state); + chv_enable_pll(new_crtc_state); } else { - vlv_prepare_pll(crtc, new_crtc_state); - vlv_enable_pll(crtc, new_crtc_state); + vlv_prepare_pll(new_crtc_state); + vlv_enable_pll(new_crtc_state); } intel_encoders_pre_enable(state, crtc); @@ -3998,7 +3998,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_enable(state, crtc); - i9xx_enable_pll(crtc, new_crtc_state); + i9xx_enable_pll(new_crtc_state); i9xx_pfit_enable(new_crtc_state); @@ -7272,7 +7272,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, dev_priv->display.crtc_compute_clock && !crtc_state->bigjoiner_slave && !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { - ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); + ret = dev_priv->display.crtc_compute_clock(crtc_state); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 13ed2711b97a..b27922ca109b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -777,10 +777,10 @@ static u32 pnv_dpll_compute_fp(const struct dpll *dpll) return (1 << dpll->n) << 16 | dpll->m2; } -static void i9xx_update_pll_dividers(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state, +static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; u32 fp, fp2 = 0; @@ -805,15 +805,15 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc, } } -static void i9xx_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state, +static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; u32 dpll; - i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); + i9xx_update_pll_dividers(crtc_state, reduced_clock); dpll = DPLL_VGA_MODE_DIS; @@ -878,16 +878,15 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, } } -static void i8xx_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state, +static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; u32 dpll; - i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); + i9xx_update_pll_dividers(crtc_state, reduced_clock); dpll = DPLL_VGA_MODE_DIS; @@ -928,9 +927,9 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc, crtc_state->dpll_hw_state.dpll = dpll; } -static int hsw_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); @@ -956,10 +955,10 @@ static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) return i9xx_dpll_compute_m(dpll) < factor * dpll->n; } -static void ilk_update_pll_dividers(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state, +static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; u32 fp, fp2 = 0; @@ -993,15 +992,15 @@ static void ilk_update_pll_dividers(struct intel_crtc *crtc, crtc_state->dpll_hw_state.fp1 = reduced_clock ? fp2 : fp; } -static void ilk_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state, +static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, const struct dpll *reduced_clock) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; u32 dpll; - ilk_update_pll_dividers(crtc, crtc_state, reduced_clock); + ilk_update_pll_dividers(crtc_state, reduced_clock); dpll = 0; @@ -1069,9 +1068,9 @@ static void ilk_compute_dpll(struct intel_crtc *crtc, crtc_state->dpll_hw_state.dpll = dpll; } -static int ilk_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); @@ -1116,7 +1115,7 @@ static int ilk_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - ilk_compute_dpll(crtc, crtc_state, NULL); + ilk_compute_dpll(crtc_state, NULL); if (!intel_reserve_shared_dplls(state, crtc, NULL)) { drm_dbg_kms(&dev_priv->drm, @@ -1128,9 +1127,10 @@ static int ilk_crtc_compute_clock(struct intel_crtc *crtc, return 0; } -void vlv_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +void vlv_compute_dpll(struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (crtc->pipe != PIPE_A) @@ -1145,9 +1145,10 @@ void vlv_compute_dpll(struct intel_crtc *crtc, (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; } -void chv_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config) +void chv_compute_dpll(struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (crtc->pipe != PIPE_A) @@ -1161,8 +1162,7 @@ void chv_compute_dpll(struct intel_crtc *crtc, (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; } -static int chv_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state) { int refclk = 100000; const struct intel_limit *limit = &intel_limits_chv; @@ -1178,13 +1178,12 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - chv_compute_dpll(crtc, crtc_state); + chv_compute_dpll(crtc_state); return 0; } -static int vlv_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state) { int refclk = 100000; const struct intel_limit *limit = &intel_limits_vlv; @@ -1200,14 +1199,14 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - vlv_compute_dpll(crtc, crtc_state); + vlv_compute_dpll(crtc_state); return 0; } -static int g4x_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_limit *limit; int refclk = 96000; @@ -1245,16 +1244,15 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - i9xx_compute_dpll(crtc, crtc_state, NULL); + i9xx_compute_dpll(crtc_state, NULL); return 0; } -static int pnv_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_limit *limit; int refclk = 96000; @@ -1282,16 +1280,15 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - i9xx_compute_dpll(crtc, crtc_state, NULL); + i9xx_compute_dpll(crtc_state, NULL); return 0; } -static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_limit *limit; int refclk = 96000; @@ -1319,16 +1316,15 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - i9xx_compute_dpll(crtc, crtc_state, NULL); + i9xx_compute_dpll(crtc_state, NULL); return 0; } -static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state) +static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct intel_limit *limit; int refclk = 48000; @@ -1358,7 +1354,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, return -EINVAL; } - i8xx_compute_dpll(crtc, crtc_state, NULL); + i8xx_compute_dpll(crtc_state, NULL); return 0; } @@ -1392,9 +1388,9 @@ static bool i9xx_has_pps(struct drm_i915_private *dev_priv) return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); } -void i9xx_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state) +void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); i915_reg_t reg = DPLL(crtc->pipe); u32 dpll = crtc_state->dpll_hw_state.dpll; @@ -1467,9 +1463,9 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); } -static void _vlv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +static void _vlv_enable_pll(const struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; @@ -1481,9 +1477,9 @@ static void _vlv_enable_pll(struct intel_crtc *crtc, drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); } -void vlv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +void vlv_enable_pll(const struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; @@ -1493,7 +1489,7 @@ void vlv_enable_pll(struct intel_crtc *crtc, assert_panel_unlocked(dev_priv, pipe); if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) - _vlv_enable_pll(crtc, pipe_config); + _vlv_enable_pll(pipe_config); intel_de_write(dev_priv, DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); @@ -1501,9 +1497,9 @@ void vlv_enable_pll(struct intel_crtc *crtc, } -static void _chv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +static void _chv_enable_pll(const struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; enum dpio_channel port = vlv_pipe_to_channel(pipe); @@ -1531,9 +1527,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc, drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); } -void chv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +void chv_enable_pll(const struct intel_crtc_state *pipe_config) { + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; @@ -1543,7 +1539,7 @@ void chv_enable_pll(struct intel_crtc *crtc, assert_panel_unlocked(dev_priv, pipe); if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) - _chv_enable_pll(crtc, pipe_config); + _chv_enable_pll(pipe_config); if (pipe != PIPE_A) { /* @@ -1572,11 +1568,10 @@ void chv_enable_pll(struct intel_crtc *crtc, } } -void vlv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +void vlv_prepare_pll(const struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 mdiv; u32 bestn, bestm1, bestm2, bestp1, bestp2; @@ -1671,11 +1666,10 @@ void vlv_prepare_pll(struct intel_crtc *crtc, vlv_dpio_put(dev_priv); } -void chv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) +void chv_prepare_pll(const struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; enum dpio_channel port = vlv_pipe_to_channel(pipe); u32 loopfilter, tribuf_calcntr; @@ -1802,13 +1796,13 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, pipe_config->output_types = BIT(INTEL_OUTPUT_EDP); if (IS_CHERRYVIEW(dev_priv)) { - chv_compute_dpll(crtc, pipe_config); - chv_prepare_pll(crtc, pipe_config); - chv_enable_pll(crtc, pipe_config); + chv_compute_dpll(pipe_config); + chv_prepare_pll(pipe_config); + chv_enable_pll(pipe_config); } else { - vlv_compute_dpll(crtc, pipe_config); - vlv_prepare_pll(crtc, pipe_config); - vlv_enable_pll(crtc, pipe_config); + vlv_compute_dpll(pipe_config); + vlv_prepare_pll(pipe_config); + vlv_enable_pll(pipe_config); } kfree(pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index e2f845902abf..29f31075cdf0 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -19,27 +19,20 @@ int vlv_calc_dpll_params(int refclk, struct dpll *clock); int pnv_calc_dpll_params(int refclk, struct dpll *clock); int i9xx_calc_dpll_params(int refclk, struct dpll *clock); u32 i9xx_dpll_compute_fp(const struct dpll *dpll); -void vlv_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config); -void chv_compute_dpll(struct intel_crtc *crtc, - struct intel_crtc_state *pipe_config); +void vlv_compute_dpll(struct intel_crtc_state *crtc_state); +void chv_compute_dpll(struct intel_crtc_state *crtc_state); int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, const struct dpll *dpll); void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe); -void i9xx_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state); -void vlv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); -void chv_enable_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); +void i9xx_enable_pll(const struct intel_crtc_state *crtc_state); +void vlv_enable_pll(const struct intel_crtc_state *crtc_state); +void chv_enable_pll(const struct intel_crtc_state *crtc_state); void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe); void i9xx_disable_pll(const struct intel_crtc_state *crtc_state); -void vlv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); -void chv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); +void vlv_prepare_pll(const struct intel_crtc_state *crtc_state); +void chv_prepare_pll(const struct intel_crtc_state *crtc_state); bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, struct dpll *best_clock); int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index da5f230e2d4b..02a2ab00a409 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -352,8 +352,7 @@ struct drm_i915_display_funcs { struct intel_crtc_state *); void (*get_initial_plane_config)(struct intel_crtc *, struct intel_initial_plane_config *); - int (*crtc_compute_clock)(struct intel_crtc *crtc, - struct intel_crtc_state *crtc_state); + int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state); void (*crtc_enable)(struct intel_atomic_state *state, struct intel_crtc *crtc); void (*crtc_disable)(struct intel_atomic_state *state,

[05/13] drm/i915: Clean dpll calling convention

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