From patchwork Thu Jul 15 09:35:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12379689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97E9EC07E96 for ; Thu, 15 Jul 2021 09:35:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30AA76136E for ; Thu, 15 Jul 2021 09:35:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 30AA76136E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E379F6E7FA; Thu, 15 Jul 2021 09:35:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78B426E7FA for ; Thu, 15 Jul 2021 09:35:56 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10045"; a="208696953" X-IronPort-AV: E=Sophos;i="5.84,240,1620716400"; d="scan'208";a="208696953" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2021 02:35:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,240,1620716400"; d="scan'208";a="413084737" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 15 Jul 2021 02:35:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Thu, 15 Jul 2021 12:35:53 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Thu, 15 Jul 2021 12:35:25 +0300 Message-Id: <20210715093530.31711-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210715093530.31711-1-ville.syrjala@linux.intel.com> References: <20210715093530.31711-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/13] drm/i915: Program DPLL P1 dividers consistently X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä On g4x and pch the DPLL has two P1 dividers (for refresh rate switching). Program the FPx1 P1 divider consistently to the reduced clock P1 divider if available, otherwise just program it to the same value as the FPx0 P1 divider. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpll.c | 80 ++++++++++++----------- 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 2f6903ec0a9f..0df9daf4dbf2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -778,42 +778,34 @@ static u32 pnv_dpll_compute_fp(const struct dpll *dpll) } static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, + const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct dpll *clock = &crtc_state->dpll; - u32 fp, fp2 = 0; + u32 fp, fp2; if (IS_PINEVIEW(dev_priv)) { fp = pnv_dpll_compute_fp(clock); - if (reduced_clock) - fp2 = pnv_dpll_compute_fp(reduced_clock); + fp2 = pnv_dpll_compute_fp(reduced_clock); } else { fp = i9xx_dpll_compute_fp(clock); - if (reduced_clock) - fp2 = i9xx_dpll_compute_fp(reduced_clock); + fp2 = i9xx_dpll_compute_fp(reduced_clock); } crtc_state->dpll_hw_state.fp0 = fp; - - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && - reduced_clock) { - crtc_state->dpll_hw_state.fp1 = fp2; - } else { - crtc_state->dpll_hw_state.fp1 = fp; - } + crtc_state->dpll_hw_state.fp1 = fp2; } static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, + const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct dpll *clock = &crtc_state->dpll; u32 dpll; - i9xx_update_pll_dividers(crtc_state, reduced_clock); + i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); dpll = DPLL_VGA_MODE_DIS; @@ -836,13 +828,17 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, dpll |= DPLL_SDVO_HIGH_SPEED; /* compute bitmask from p1 value */ - if (IS_PINEVIEW(dev_priv)) + if (IS_G4X(dev_priv)) { + dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; + dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + } else if (IS_PINEVIEW(dev_priv)) { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; - else { + WARN_ON(reduced_clock->p1 != clock->p1); + } else { dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; - if (IS_G4X(dev_priv) && reduced_clock) - dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + WARN_ON(reduced_clock->p1 != clock->p1); } + switch (clock->p2) { case 5: dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; @@ -857,6 +853,8 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } + WARN_ON(reduced_clock->p2 != clock->p2); + if (DISPLAY_VER(dev_priv) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); @@ -879,14 +877,14 @@ static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, } static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, + const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct dpll *clock = &crtc_state->dpll; u32 dpll; - i9xx_update_pll_dividers(crtc_state, reduced_clock); + i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); dpll = DPLL_VGA_MODE_DIS; @@ -900,6 +898,8 @@ static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, if (clock->p2 == 4) dpll |= PLL_P2_DIVIDE_BY_4; } + WARN_ON(reduced_clock->p1 != clock->p1); + WARN_ON(reduced_clock->p2 != clock->p2); /* * Bspec: @@ -956,12 +956,12 @@ static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) } static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, + const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct dpll *clock = &crtc_state->dpll; - u32 fp, fp2 = 0; + u32 fp, fp2; int factor; /* Enable autotuning of the PLL clock (if permissible) */ @@ -977,30 +977,26 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, } fp = i9xx_dpll_compute_fp(clock); - if (ilk_needs_fb_cb_tune(clock, factor)) fp |= FP_CB_TUNE; - if (reduced_clock) { - fp2 = i9xx_dpll_compute_fp(reduced_clock); - - if (reduced_clock->m < factor * reduced_clock->n) - fp2 |= FP_CB_TUNE; - } + fp2 = i9xx_dpll_compute_fp(reduced_clock); + if (reduced_clock->m < factor * reduced_clock->n) + fp2 |= FP_CB_TUNE; crtc_state->dpll_hw_state.fp0 = fp; - crtc_state->dpll_hw_state.fp1 = reduced_clock ? fp2 : fp; + crtc_state->dpll_hw_state.fp1 = fp2; } static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, + const struct dpll *clock, const struct dpll *reduced_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct dpll *clock = &crtc_state->dpll; u32 dpll; - ilk_update_pll_dividers(crtc_state, reduced_clock); + ilk_update_pll_dividers(crtc_state, clock, reduced_clock); dpll = 0; @@ -1040,7 +1036,7 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, /* compute bitmask from p1 value */ dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; /* also FPA1 */ - dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; + dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; switch (clock->p2) { case 5: @@ -1056,6 +1052,7 @@ static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } + WARN_ON(reduced_clock->p2 != clock->p2); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && intel_panel_use_ssc(dev_priv)) @@ -1115,7 +1112,8 @@ static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state) return -EINVAL; } - ilk_compute_dpll(crtc_state, NULL); + ilk_compute_dpll(crtc_state, &crtc_state->dpll, + &crtc_state->dpll); if (!intel_reserve_shared_dplls(state, crtc, NULL)) { drm_dbg_kms(&dev_priv->drm, @@ -1244,7 +1242,8 @@ static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state) return -EINVAL; } - i9xx_compute_dpll(crtc_state, NULL); + i9xx_compute_dpll(crtc_state, &crtc_state->dpll, + &crtc_state->dpll); return 0; } @@ -1280,7 +1279,8 @@ static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state) return -EINVAL; } - i9xx_compute_dpll(crtc_state, NULL); + i9xx_compute_dpll(crtc_state, &crtc_state->dpll, + &crtc_state->dpll); return 0; } @@ -1316,7 +1316,8 @@ static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) return -EINVAL; } - i9xx_compute_dpll(crtc_state, NULL); + i9xx_compute_dpll(crtc_state, &crtc_state->dpll, + &crtc_state->dpll); return 0; } @@ -1354,7 +1355,8 @@ static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) return -EINVAL; } - i8xx_compute_dpll(crtc_state, NULL); + i8xx_compute_dpll(crtc_state, &crtc_state->dpll, + &crtc_state->dpll); return 0; }