| Message ID | 20210717011227.204494-4-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/4] drm/i915/display: Disable FBC when PSR2 is enabled for xelpd platforms | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of José > Roberto de Souza > Sent: Friday, July 16, 2021 6:12 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 4/4] drm/i915/display/psr2: Force a PSR exit in > the frontbuffer modification flushes > > The CURSURFLIVE() write do not works with PSR2 selective fetch, the only > way to update screen is to program PSR2 plane and transcoder registers > during the vblank. > > We could use the frontbuffer dirty areas set by userspace with > drmModeDirtyFB() but we would still need to wait for the vblank to properly > update the PSR2 registers. > What I think is not worthy the development time considering that there is so > few userspace applications that makes use of this old method. > > So here forcing a PSR exit in this case, this will guaratee that panel will be s/ guaratee/ guarantee > properly updated. > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 1c41042841fb1..7316967aba94b 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1448,7 +1448,7 @@ static void psr_force_hw_tracking_exit(struct > intel_dp *intel_dp) { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - if (DISPLAY_VER(dev_priv) >= 9) > + if (DISPLAY_VER(dev_priv) >= 9 && > +!intel_dp->psr.psr2_sel_fetch_enabled) > /* > * Display WA #0884: skl+ > * This documented WA for bxt can be safely applied > -- > 2.32.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1c41042841fb1..7316967aba94b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1448,7 +1448,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(dev_priv) >= 9 && !intel_dp->psr.psr2_sel_fetch_enabled) /* * Display WA #0884: skl+ * This documented WA for bxt can be safely applied
The CURSURFLIVE() write do not works with PSR2 selective fetch, the only way to update screen is to program PSR2 plane and transcoder registers during the vblank. We could use the frontbuffer dirty areas set by userspace with drmModeDirtyFB() but we would still need to wait for the vblank to properly update the PSR2 registers. What I think is not worthy the development time considering that there is so few userspace applications that makes use of this old method. So here forcing a PSR exit in this case, this will guaratee that panel will be properly updated. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)