From patchwork Thu Jul 22 10:25:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 12393789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 390F7C6377D for ; Thu, 22 Jul 2021 10:19:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 092E561285 for ; Thu, 22 Jul 2021 10:19:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 092E561285 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A9B36E8BA; Thu, 22 Jul 2021 10:19:00 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D84296E14F for ; Thu, 22 Jul 2021 10:18:54 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10052"; a="275432495" X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="275432495" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2021 03:18:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="632937103" Received: from shawnle1-build-machine.itwn.intel.com ([10.5.253.12]) by orsmga005.jf.intel.com with ESMTP; 22 Jul 2021 03:18:52 -0700 From: Lee Shawn C To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Jul 2021 18:25:56 +0800 Message-Id: <20210722102558.362-4-shawn.c.lee@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210722102558.362-1-shawn.c.lee@intel.com> References: <20210722102558.362-1-shawn.c.lee@intel.com> Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915/dsi: wait for header and payload credit available X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cooper.chiou@intel.com, william.tseng@intel.com, jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Driver should wait for free header or payload buffer in FIFO. It would be good to wait a while for HW to release credit before give it up to write to HW. Without sending initailize command sets completely. It would caused MIPI display can't light up properly. Cc: Ville Syrjala Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Cooper Chiou Cc: William Tseng Signed-off-by: Lee Shawn C --- drivers/gpu/drm/i915/display/icl_dsi.c | 40 ++++++++++++-------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 43ec7fcd3f5d..1780830d9909 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -54,20 +54,28 @@ static int payload_credits_available(struct drm_i915_private *dev_priv, >> FREE_PLOAD_CREDIT_SHIFT; } -static void wait_for_header_credits(struct drm_i915_private *dev_priv, - enum transcoder dsi_trans) +static bool wait_for_header_credits(struct drm_i915_private *dev_priv, + enum transcoder dsi_trans, int hdr_credit) { if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= - MAX_HEADER_CREDIT, 100)) + hdr_credit, 100)) { drm_err(&dev_priv->drm, "DSI header credits not released\n"); + return false; + } + + return true; } -static void wait_for_payload_credits(struct drm_i915_private *dev_priv, - enum transcoder dsi_trans) +static bool wait_for_payload_credits(struct drm_i915_private *dev_priv, + enum transcoder dsi_trans, int payld_credit) { if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= - MAX_PLOAD_CREDIT, 100)) + payld_credit, 100)) { drm_err(&dev_priv->drm, "DSI payload credits not released\n"); + return false; + } + + return true; } static enum transcoder dsi_port_to_transcoder(enum port port) @@ -90,8 +98,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) /* wait for header/payload credits to be released */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - wait_for_header_credits(dev_priv, dsi_trans); - wait_for_payload_credits(dev_priv, dsi_trans); + wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); + wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT); } /* send nop DCS command */ @@ -108,7 +116,7 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) /* wait for header credits to be released */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - wait_for_header_credits(dev_priv, dsi_trans); + wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT); } /* wait for LP TX in progress bit to be cleared */ @@ -126,18 +134,13 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, struct intel_dsi *intel_dsi = host->intel_dsi; struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); - int free_credits; int i, j; for (i = 0; i < len; i += 4) { u32 tmp = 0; - free_credits = payload_credits_available(dev_priv, dsi_trans); - if (free_credits < 1) { - drm_err(&dev_priv->drm, - "Payload credit not available\n"); + if (!wait_for_payload_credits(dev_priv, dsi_trans, 1)) return false; - } for (j = 0; j < min_t(u32, len - i, 4); j++) tmp |= *data++ << 8 * j; @@ -155,15 +158,10 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); u32 tmp; - int free_credits; /* check if header credit available */ - free_credits = header_credits_available(dev_priv, dsi_trans); - if (free_credits < 1) { - drm_err(&dev_priv->drm, - "send pkt header failed, not enough hdr credits\n"); + if (!wait_for_header_credits(dev_priv, dsi_trans, 1)) return -1; - } tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));