| Message ID | 20210729170008.2836648-9-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Begin enabling Xe_HP SDV and DG2 platforms | expand |
On Thu, 2021-07-29 at 09:59 -0700, Matt Roper wrote: > From: Matthew Auld <matthew.auld@intel.com> > > Xe_HP no longer has "slices" in the same way that old platforms did. > There are new concepts (gslices, cslices, mslices) that apply in various > contexts, but for the purposes of fusing slices no longer exist and we > just have one large pool of dual-subslices (DSS) to work with. > Furthermore, the meaning of the DSS fuse is inverted compared to past > platforms --- it now specifies which DSS are enabled rather than which > ones are disabled. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Prasad Nallani <prasad.nallani@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_sseu.c | 24 ++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_getparam.c | 6 ++++-- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 3 files changed, 27 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c > index bbed8e8625e1..5d1b7d06c96b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c > @@ -139,17 +139,33 @@ static void gen12_sseu_info_init(struct intel_gt *gt) > * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. > * Instead of splitting these, provide userspace with an array > * of DSS to more closely represent the hardware resource. > + * > + * In addition, the concept of slice has been removed in Xe_HP. > + * To be compatible with prior generations, assume a single slice > + * across the entire device. Then calculate out the DSS for each > + * workload type within that software slice. > */ > intel_sseu_set_info(sseu, 1, 6, 16); > > - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > - GEN11_GT_S_ENA_MASK; > + /* > + * As mentioned above, Xe_HP does not have the concept of a slice. > + * Enable one for software backwards compatibility. > + */ > + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) > + s_en = 0x1; > + else > + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & > + GEN11_GT_S_ENA_MASK; > > dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); > > /* one bit per pair of EUs */ > - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > - GEN11_EU_DIS_MASK); > + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) > + eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; > + else > + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & > + GEN11_EU_DIS_MASK); > + > for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) > if (eu_en_fuse & BIT(eu)) > eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); > diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c > index 24e18219eb50..e289397d9178 100644 > --- a/drivers/gpu/drm/i915/i915_getparam.c > +++ b/drivers/gpu/drm/i915/i915_getparam.c > @@ -15,7 +15,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, > struct pci_dev *pdev = to_pci_dev(dev->dev); > const struct sseu_dev_info *sseu = &i915->gt.info.sseu; > drm_i915_getparam_t *param = data; > - int value; > + int value = 0; > > switch (param->param) { > case I915_PARAM_IRQ_ACTIVE: > @@ -150,7 +150,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, > return -ENODEV; > break; > case I915_PARAM_SUBSLICE_MASK: > - value = sseu->subslice_mask[0]; > + /* Only copy bits from the first slice */ > + memcpy(&value, sseu->subslice_mask, > + min(sseu->ss_stride, (u8)sizeof(value))); > if (!value) > return -ENODEV; > break; > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 62af453c8c54..99858bc593f0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3225,6 +3225,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define GEN12_GT_DSS_ENABLE _MMIO(0x913C) > > +#define XEHP_EU_ENABLE _MMIO(0x9134) > +#define XEHP_EU_ENA_MASK 0xFF > + > #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) > #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) > #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index bbed8e8625e1..5d1b7d06c96b 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -139,17 +139,33 @@ static void gen12_sseu_info_init(struct intel_gt *gt) * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. * Instead of splitting these, provide userspace with an array * of DSS to more closely represent the hardware resource. + * + * In addition, the concept of slice has been removed in Xe_HP. + * To be compatible with prior generations, assume a single slice + * across the entire device. Then calculate out the DSS for each + * workload type within that software slice. */ intel_sseu_set_info(sseu, 1, 6, 16); - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & - GEN11_GT_S_ENA_MASK; + /* + * As mentioned above, Xe_HP does not have the concept of a slice. + * Enable one for software backwards compatibility. + */ + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) + s_en = 0x1; + else + s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & + GEN11_GT_S_ENA_MASK; dss_en = intel_uncore_read(uncore, GEN12_GT_DSS_ENABLE); /* one bit per pair of EUs */ - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & - GEN11_EU_DIS_MASK); + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) + eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; + else + eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & + GEN11_EU_DIS_MASK); + for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) if (eu_en_fuse & BIT(eu)) eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c index 24e18219eb50..e289397d9178 100644 --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c @@ -15,7 +15,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, struct pci_dev *pdev = to_pci_dev(dev->dev); const struct sseu_dev_info *sseu = &i915->gt.info.sseu; drm_i915_getparam_t *param = data; - int value; + int value = 0; switch (param->param) { case I915_PARAM_IRQ_ACTIVE: @@ -150,7 +150,9 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data, return -ENODEV; break; case I915_PARAM_SUBSLICE_MASK: - value = sseu->subslice_mask[0]; + /* Only copy bits from the first slice */ + memcpy(&value, sseu->subslice_mask, + min(sseu->ss_stride, (u8)sizeof(value))); if (!value) return -ENODEV; break; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 62af453c8c54..99858bc593f0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3225,6 +3225,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN12_GT_DSS_ENABLE _MMIO(0x913C) +#define XEHP_EU_ENABLE _MMIO(0x9134) +#define XEHP_EU_ENA_MASK 0xFF + #define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)