From patchwork Mon Aug 16 04:52:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Siddiqui, Ayaz A" X-Patchwork-Id: 12437725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D615FC4338F for ; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A21B5613AC for ; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A21B5613AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02C0D8995F; Mon, 16 Aug 2021 04:55:56 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBCB989BCD for ; Mon, 16 Aug 2021 04:55:42 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10077"; a="215823999" X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="215823999" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2021 21:55:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,324,1620716400"; d="scan'208";a="422739342" Received: from ayazahma-nuc8i7beh.iind.intel.com ([10.145.162.59]) by orsmga006.jf.intel.com with ESMTP; 15 Aug 2021 21:55:40 -0700 From: Ayaz A Siddiqui To: intel-gfx@lists.freedesktop.org Cc: Ayaz A Siddiqui , CQ Tang Date: Mon, 16 Aug 2021 10:22:25 +0530 Message-Id: <20210816045229.423234-2-ayaz.siddiqui@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210816045229.423234-1-ayaz.siddiqui@intel.com> References: <20210816045229.423234-1-ayaz.siddiqui@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH V2 1/5] drm/i915/gt: Add support of mocs propagation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Now there are lots of Command and registers that require mocs index programming. So propagating mocs_index from mocs to gt so that it can be used directly without having platform-specific checks. Signed-off-by: Ayaz A Siddiqui Reviewed-by: CQ Tang --- drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_mocs.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index a81e21bf1bd1a..88601a2d2c229 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -192,6 +192,10 @@ struct intel_gt { unsigned long mslice_mask; } info; + + struct i915_mocs_index_gt { + u8 uc_index; + } mocs; }; enum intel_gt_scratch_field { diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 582c4423b95d6..10cc508c1a4f6 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -22,6 +22,7 @@ struct drm_i915_mocs_table { unsigned int size; unsigned int n_entries; const struct drm_i915_mocs_entry *table; + u8 uc_index; }; /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ @@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, { unsigned int flags; + memset(table, 0, sizeof(struct drm_i915_mocs_table)); + if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; @@ -504,6 +507,12 @@ static u32 global_mocs_offset(void) return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0)); } +static void set_mocs_index(struct intel_gt *gt, + struct drm_i915_mocs_table *table) +{ + gt->mocs.uc_index = table->uc_index; +} + void intel_mocs_init(struct intel_gt *gt) { struct drm_i915_mocs_table table; @@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt) flags = get_mocs_settings(gt->i915, &table); if (flags & HAS_GLOBAL_MOCS) __init_mocs_table(gt->uncore, &table, global_mocs_offset()); + set_mocs_index(gt, &table); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)