diff mbox series

[09/27] drm/i915/guc: Kick tasklet after queuing a request

Message ID	20210826032327.18078-10-matthew.brost@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=HVxp=NR=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EDC6A610A7 From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: <daniele.ceraolospurio@intel.com> Date: Wed, 25 Aug 2021 20:23:09 -0700 Message-Id: <20210826032327.18078-10-matthew.brost@intel.com> In-Reply-To: <20210826032327.18078-1-matthew.brost@intel.com> References: <20210826032327.18078-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 09/27] drm/i915/guc: Kick tasklet after queuing a request Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	Clean up GuC CI failures, simplify locking, and kernel DOC \| expand [00/27] Clean up GuC CI failures, simplify locking, and kernel DOC [01/27] drm/i915/guc: Fix blocked context accounting [02/27] drm/i915/guc: Fix outstanding G2H accounting [03/27] drm/i915/guc: Unwind context requests in reverse order [04/27] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context [05/27] drm/i915/guc: Process all G2H message at once in work queue [06/27] drm/i915/guc: Workaround reset G2H is received after schedule done G2H [07/27] Revert "drm/i915/gt: Propagate change in error status to children on unhold" [08/27] drm/i915/selftests: Add a cancel request selftest that triggers a reset [09/27] drm/i915/guc: Kick tasklet after queuing a request [10/27] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered [11/27] drm/i915/guc: Copy whole golden context, set engine state size of subset [12/27] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H [13/27] drm/i915/guc: Take context ref when cancelling request [14/27] drm/i915/guc: Don't touch guc_state.sched_state without a lock [15/27] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV [16/27] drm/i915: Allocate error capture in nowait context [17/27] drm/i915/guc: Flush G2H work queue during reset [18/27] drm/i915/guc: Release submit fence from an irq_work [19/27] drm/i915/guc: Move guc_blocked fence to struct guc_state [20/27] drm/i915/guc: Rework and simplify locking [21/27] drm/i915/guc: Proper xarray usage for contexts_lookup [22/27] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin [23/27] drm/i915/guc: Move GuC priority fields in context under guc_active [24/27] drm/i915/guc: Move fields protected by guc->contexts_lock into sub structure [25/27] drm/i915/guc: Drop guc_active move everything into guc_state [26/27] drm/i915/guc: Add GuC kernel doc [27/27] drm/i915/guc: Drop static inline functions intel_guc_submission.c

Commit Message

Matthew Brost Aug. 26, 2021, 3:23 a.m. UTC

Kick tasklet after queuing a request so it submitted in a timely manner.

Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new inteface")
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 592b421e1429..b30fdccc71d4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1047,6 +1047,7 @@  static inline void queue_request(struct i915_sched_engine *sched_engine,
 	list_add_tail(&rq->sched.link,
 		      i915_sched_lookup_priolist(sched_engine, prio));
 	set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+	tasklet_hi_schedule(&sched_engine->tasklet);
 }
 
 static int guc_bypass_tasklet_submit(struct intel_guc *guc,