| Message ID | 20210902121429.27606-4-shawn.c.lee@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSI driver improvement | expand |
On Thu, 02 Sep 2021, Lee Shawn C <shawn.c.lee@intel.com> wrote: > VDSC engine can process only 1 pixel per Cd clock. In case > VDSC is used and max slice count == 1, max supported pixel > clock should be 100% of CD clock. Then do min_cdclk and > pixel clock comparison to get proper min cdclk. > > v2: > - Check for dsc enable and slice count ==1 then allow to > double confirm min cdclk value. > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Cc: Cooper Chiou <cooper.chiou@intel.com> > Cc: William Tseng <william.tseng@intel.com> > Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> > Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 34fa4130d5c4..9aec17b33819 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > /* Account for additional needs from the planes */ > min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); > > + /* > + * VDSC engine can process only 1 pixel per Cd clock. > + * In case VDSC is used and max slice count == 1, > + * max supported pixel clock should be 100% of CD clock. > + * Then do min_cdclk and pixel clock comparison to get cdclk. > + */ To elaborate, we can't use two VDSC engines to reach an effective 2 ppc when the slice count is 1, and are thus limited to 1 ppc. > + if (crtc_state->dsc.compression_enable && > + crtc_state->dsc.slice_count == 1) > + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); Acked-by: Jani Nikula <jani.nikula@intel.com> This is the immediate fix, but I think we'll need to improve this later on. In some cases, especially with DP and maybe not so much with DSI, we may have cases where the min_cdclk will now exceed the max_cdclk and fail the compute config. In that case, we should do a better job of pruning the mode up front instead of letting userspace think it's okay, only to fail it at this stage. We should probably also abstract the ppc limitations in the DSC code better, instead of having them leak here. BR, Jani. > + > /* > * HACK. Currently for TGL platforms we calculate > * min_cdclk initially based on pixel_rate divided
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 34fa4130d5c4..9aec17b33819 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); + /* + * VDSC engine can process only 1 pixel per Cd clock. + * In case VDSC is used and max slice count == 1, + * max supported pixel clock should be 100% of CD clock. + * Then do min_cdclk and pixel clock comparison to get cdclk. + */ + if (crtc_state->dsc.compression_enable && + crtc_state->dsc.slice_count == 1) + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); + /* * HACK. Currently for TGL platforms we calculate * min_cdclk initially based on pixel_rate divided