| Message ID | 20210910031741.3292388-8-airlied@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/25] drm/i915/uncore: split the fw get function into separate vfunc | expand |
On Fri, 10 Sep 2021, Dave Airlie <airlied@gmail.com> wrote: > From: Dave Airlie <airlied@redhat.com> > > This wraps the fdi link training vfunc to make it clearer. > > Suggested by Jani. > > Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > drivers/gpu/drm/i915/display/intel_fdi.c | 8 ++++++++ > drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++ > 3 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 71518e71591b..aa174192c279 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, > assert_pch_transcoder_disabled(dev_priv, pipe); > > /* For PCH output, training FDI link */ > - dev_priv->display.fdi_link_train(crtc, crtc_state); > + intel_fdi_link_train(crtc, crtc_state); > > /* We need to program the right clock selection before writing the pixel > * mutliplier into the DPLL. */ > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c > index fc09b781f15f..339243399a65 100644 > --- a/drivers/gpu/drm/i915/display/intel_fdi.c > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c > @@ -10,6 +10,14 @@ > #include "intel_fdi.h" > #include "intel_sideband.h" > > +void intel_fdi_link_train(struct intel_crtc *crtc, > + const struct intel_crtc_state *crtc_state) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + > + dev_priv->display.fdi_link_train(crtc, crtc_state); > +} > + > /* units of 100MHz */ > static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) > { > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h > index 60acf2133145..61cb216a09f5 100644 > --- a/drivers/gpu/drm/i915/display/intel_fdi.h > +++ b/drivers/gpu/drm/i915/display/intel_fdi.h > @@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, > void intel_fdi_pll_freq_update(struct drm_i915_private *i915); > void lpt_fdi_program_mphy(struct drm_i915_private *i915); > > +void intel_fdi_link_train(struct intel_crtc *crtc, > + const struct intel_crtc_state *crtc_state); > #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 71518e71591b..aa174192c279 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, assert_pch_transcoder_disabled(dev_priv, pipe); /* For PCH output, training FDI link */ - dev_priv->display.fdi_link_train(crtc, crtc_state); + intel_fdi_link_train(crtc, crtc_state); /* We need to program the right clock selection before writing the pixel * mutliplier into the DPLL. */ diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index fc09b781f15f..339243399a65 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -10,6 +10,14 @@ #include "intel_fdi.h" #include "intel_sideband.h" +void intel_fdi_link_train(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + dev_priv->display.fdi_link_train(crtc, crtc_state); +} + /* units of 100MHz */ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h index 60acf2133145..61cb216a09f5 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.h +++ b/drivers/gpu/drm/i915/display/intel_fdi.h @@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, void intel_fdi_pll_freq_update(struct drm_i915_private *i915); void lpt_fdi_program_mphy(struct drm_i915_private *i915); +void intel_fdi_link_train(struct intel_crtc *crtc, + const struct intel_crtc_state *crtc_state); #endif