Message ID | 20210921152517.803-4-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915/fbc: Rework CFB stride/size calculations | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index ff05eb83e204..1e7d86f04fe9 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -94,6 +94,13 @@ static unsigned int skl_fbc_min_cfb_stride(const struct intel_fbc_state_cache *c /* minimum segment stride we can use */ stride = cache->plane.src_w * cpp * height / limit; + /* + * Wa_16011863758: icl+ + * Avoid some hardware segment address miscalculation. + */ + if (DISPLAY_VER(i915) >= 11) + stride += 64; + /* * At least some of the platforms require each 4 line segment to * be 512 byte aligned. Just do it always for simplicity.