diff mbox series

[2/3] drm/dp: reuse the 8b/10b link training delay helpers

Message ID 20211014150059.28957-2-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/3] drm/dp: add helpers to read link training delays | expand

Commit Message

Jani Nikula Oct. 14, 2021, 3 p.m. UTC 
Reuse the 8b/10b link training delay helpers. Functionally this skips
the check for invalid values for DPCD 1.4 and later at clock recovery
delay (as it's a fixed delay and bypasses the rd_interval) but the same
value will be checked and invalid values reported at channel
equalization.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++--------------------
 1 file changed, 10 insertions(+), 20 deletions(-)

Comments

Ville Syrjälä Oct. 14, 2021, 3:43 p.m. UTC | #1 
On Thu, Oct 14, 2021 at 06:00:58PM +0300, Jani Nikula wrote:
> Reuse the 8b/10b link training delay helpers. Functionally this skips
> the check for invalid values for DPCD 1.4 and later at clock recovery
> delay (as it's a fixed delay and bypasses the rd_interval) but the same
> value will be checked and invalid values reported at channel
> equalization.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/drm_dp_helper.c | 30 ++++++++++--------------------
>  1 file changed, 10 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index f7ebf5974fa7..ada0a1ff262d 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -284,35 +284,25 @@ EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
>  void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
>  					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  {
> -	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> -					 DP_TRAINING_AUX_RD_MASK;
> +	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +		DP_TRAINING_AUX_RD_MASK;
> +	int delay_us;
>  
> -	if (rd_interval > 4)
> -		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
> -			    aux->name, rd_interval);
> -
> -	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
> -		rd_interval = 100;
> +	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
> +		delay_us = 100;
>  	else
> -		rd_interval *= 4 * USEC_PER_MSEC;
> +		delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
>  
> -	usleep_range(rd_interval, rd_interval * 2);
> +	usleep_range(delay_us, delay_us * 2);
>  }
>  EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>  
>  static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
> -						 unsigned long rd_interval)
> +						 u8 rd_interval)
>  {
> -	if (rd_interval > 4)
> -		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
> -			    aux->name, rd_interval);
> -
> -	if (rd_interval == 0)
> -		rd_interval = 400;
> -	else
> -		rd_interval *= 4 * USEC_PER_MSEC;
> +	int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
>  
> -	usleep_range(rd_interval, rd_interval * 2);
> +	usleep_range(delay_us, delay_us * 2);
>  }
>  
>  void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
> -- 
> 2.30.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f7ebf5974fa7..ada0a1ff262d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -284,35 +284,25 @@  EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
-	unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
-					 DP_TRAINING_AUX_RD_MASK;
+	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+		DP_TRAINING_AUX_RD_MASK;
+	int delay_us;
 
-	if (rd_interval > 4)
-		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
-			    aux->name, rd_interval);
-
-	if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
-		rd_interval = 100;
+	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
+		delay_us = 100;
 	else
-		rd_interval *= 4 * USEC_PER_MSEC;
+		delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
 
-	usleep_range(rd_interval, rd_interval * 2);
+	usleep_range(delay_us, delay_us * 2);
 }
 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 
 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
-						 unsigned long rd_interval)
+						 u8 rd_interval)
 {
-	if (rd_interval > 4)
-		drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
-			    aux->name, rd_interval);
-
-	if (rd_interval == 0)
-		rd_interval = 400;
-	else
-		rd_interval *= 4 * USEC_PER_MSEC;
+	int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
 
-	usleep_range(rd_interval, rd_interval * 2);
+	usleep_range(delay_us, delay_us * 2);
 }
 
 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,