@@ -1650,7 +1650,7 @@ static void invalidate_csb_entries(const u64 *first, const u64 *last)
}
/*
- * Starting with Gen12, the status has a new format:
+ * Starting with Graphics version 12, the status has a new format:
*
* bit 0: switched to new queue
* bit 1: reserved
@@ -611,10 +611,10 @@ static const u8 dg2_rcs_offsets[] = {
static const u8 *reg_offsets(const struct intel_engine_cs *engine)
{
/*
- * The gen12+ lists only have the registers we program in the basic
- * default state. We rely on the context image using relative
- * addressing to automatic fixup the register state between the
- * physical engines for virtual engine.
+ * The graphics 12 and newer platforms, lists only have the registers we
+ * program in the basic default state. We rely on the context image
+ * using relative addressing to automatic fixup the register state
+ * between the physical engines for virtual engine.
*/
GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
!intel_engine_has_relative_mmio(engine));
Although gen12 is a valid thing for the gt side on TGL, we should prefer graphics version over the old global "gen" thing. Of course we are not changing functions and variables and the legacy there, but at least let's start to document things properly and set some good examples. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-)