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[4/4] drm/amd/display: Add DP 2.0 MST DM Support

Message ID 20211020194715.1107972-4-Bhawanpreet.Lakha@amd.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm: Remove slot checks in dp mst topology during commit | expand

Commit Message

Bhawanpreet Lakha Oct. 20, 2021, 7:47 p.m. UTC
[Why]
Add DP2 MST and debugfs support

[How]
Update the slot info based on the link encoding format

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++++++++++++++++++
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  3 ++
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  5 +++-
 3 files changed, 36 insertions(+), 1 deletion(-)

Comments

Lin, Wayne Oct. 22, 2021, 8:55 a.m. UTC | #1
[AMD Official Use Only]

Hi Bhawan,
Just a nitpick below. With that fixed, feel free to add:
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>

Thanks!

Regards,
Wayne
> -----Original Message-----
> From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Sent: Thursday, October 21, 2021 3:47 AM
> To: Zuo, Jerry <Jerry.Zuo@amd.com>; dri-devel@lists.freedesktop.org; lyude@redhat.com
> Cc: Wentland, Harry <Harry.Wentland@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Kazlauskas, Nicholas
> <Nicholas.Kazlauskas@amd.com>; Lipski, Mikita <Mikita.Lipski@amd.com>; intel-gfx@lists.freedesktop.org; Lakha, Bhawanpreet
> <Bhawanpreet.Lakha@amd.com>
> Subject: [PATCH 4/4] drm/amd/display: Add DP 2.0 MST DM Support
>
> [Why]
> Add DP2 MST and debugfs support
>
> [How]
> Update the slot info based on the link encoding format
>
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++++++++++++++++++  .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |
> 3 ++  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c |  5 +++-
>  3 files changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index e56f73e299ef..875425ee91d0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -10741,6 +10741,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,  #if defined(CONFIG_DRM_AMD_DC_DCN)
>       struct dsc_mst_fairness_vars vars[MAX_PIPES];  #endif
> +     struct drm_dp_mst_topology_state *mst_state;
> +     struct drm_dp_mst_topology_mgr *mgr;
>
>       trace_amdgpu_dm_atomic_check_begin(state);
>
> @@ -10948,6 +10950,33 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
>               lock_and_validation_needed = true;
>       }
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> +     /* set the slot info for each mst_state based on the link encoding format */
> +     for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
> +             struct amdgpu_dm_connector *aconnector;
> +             struct drm_connector *connector;
> +             struct drm_connector_list_iter iter;
> +             u8 link_coding_cap;
> +
> +             if (!mgr->mst_state )
> +                     continue;
> +
> +             drm_connector_list_iter_begin(dev, &iter);
> +             drm_for_each_connector_iter(connector, &iter) {
> +                     int id = connector->index;
> +
> +                     if (id == mst_state->mgr->conn_base_id) {
> +                             aconnector = to_amdgpu_dm_connector(connector);
> +                             link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
> +                             drm_dp_mst_update_slots(mst_state, link_coding_cap);
> +
> +                             break;
> +                     }
> +             }
> +             drm_connector_list_iter_end(&iter);
> +
> +     }
> +#endif
>       /**
>        * Streams and planes are reset when there are changes that affect
>        * bandwidth. Anything that affects bandwidth needs to go through diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> index 9b3ad56607bb..1a68a674913c 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
> @@ -294,6 +294,9 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
>       case LINK_RATE_RBR2:
>       case LINK_RATE_HIGH2:
>       case LINK_RATE_HIGH3:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> +     case LINK_RATE_UHBR10:
> +#endif
>               break;
>       default:
>               valid_input = false;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> index 6169488e2011..53b5cc7b0679 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
> @@ -219,6 +219,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
>       struct drm_dp_mst_topology_mgr *mst_mgr;
>       struct drm_dp_mst_port *mst_port;
>       bool ret;
> +     u8 link_coding_cap;
>
>       aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
>       /* Accessing the connector state is required for vcpi_slots allocation @@ -238,6 +239,8 @@ bool
> dm_helpers_dp_mst_write_payload_allocation_table(
>
>       mst_port = aconnector->port;
>
> +     link_coding_cap =
> +dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
> +
>       if (enable) {
>
>               ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, @@ -251,7 +254,7 @@ bool
> dm_helpers_dp_mst_write_payload_allocation_table(
>       }
>
>       /* It's OK for this to fail */
> -     drm_dp_update_payload_part1(mst_mgr, 1);
> +     drm_dp_update_payload_part1(mst_mgr, (link_coding_cap ==
> +DP_CAP_ANSI_128B132B) ? 0:1);
I think should have format warning here that we need space between the number and the colon .
i.e. should be "0 : 1"

>
>       /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
>        * AUX message. The sequence is slot 1-63 allocated sequence for each
> --
> 2.25.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e56f73e299ef..875425ee91d0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -10741,6 +10741,8 @@  static int amdgpu_dm_atomic_check(struct drm_device *dev,
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	struct dsc_mst_fairness_vars vars[MAX_PIPES];
 #endif
+	struct drm_dp_mst_topology_state *mst_state;
+	struct drm_dp_mst_topology_mgr *mgr;
 
 	trace_amdgpu_dm_atomic_check_begin(state);
 
@@ -10948,6 +10950,33 @@  static int amdgpu_dm_atomic_check(struct drm_device *dev,
 		lock_and_validation_needed = true;
 	}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	/* set the slot info for each mst_state based on the link encoding format */
+	for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
+		struct amdgpu_dm_connector *aconnector;
+		struct drm_connector *connector;
+		struct drm_connector_list_iter iter;
+		u8 link_coding_cap;
+
+		if (!mgr->mst_state )
+			continue;
+
+		drm_connector_list_iter_begin(dev, &iter);
+		drm_for_each_connector_iter(connector, &iter) {
+			int id = connector->index;
+
+			if (id == mst_state->mgr->conn_base_id) {
+				aconnector = to_amdgpu_dm_connector(connector);
+				link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
+				drm_dp_mst_update_slots(mst_state, link_coding_cap);
+
+				break;
+			}
+		}
+		drm_connector_list_iter_end(&iter);
+
+	}
+#endif
 	/**
 	 * Streams and planes are reset when there are changes that affect
 	 * bandwidth. Anything that affects bandwidth needs to go through
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 9b3ad56607bb..1a68a674913c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -294,6 +294,9 @@  static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 	case LINK_RATE_RBR2:
 	case LINK_RATE_HIGH2:
 	case LINK_RATE_HIGH3:
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	case LINK_RATE_UHBR10:
+#endif
 		break;
 	default:
 		valid_input = false;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 6169488e2011..53b5cc7b0679 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -219,6 +219,7 @@  bool dm_helpers_dp_mst_write_payload_allocation_table(
 	struct drm_dp_mst_topology_mgr *mst_mgr;
 	struct drm_dp_mst_port *mst_port;
 	bool ret;
+	u8 link_coding_cap;
 
 	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 	/* Accessing the connector state is required for vcpi_slots allocation
@@ -238,6 +239,8 @@  bool dm_helpers_dp_mst_write_payload_allocation_table(
 
 	mst_port = aconnector->port;
 
+	link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
+
 	if (enable) {
 
 		ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
@@ -251,7 +254,7 @@  bool dm_helpers_dp_mst_write_payload_allocation_table(
 	}
 
 	/* It's OK for this to fail */
-	drm_dp_update_payload_part1(mst_mgr, 1);
+	drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1);
 
 	/* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
 	 * AUX message. The sequence is slot 1-63 allocated sequence for each