From patchwork Fri Oct 22 04:14:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Cooper Chiou X-Patchwork-Id: 12576989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC1B6C433EF for ; Fri, 22 Oct 2021 04:24:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 021B061056 for ; Fri, 22 Oct 2021 04:22:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 021B061056 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90CDB89F4F; Fri, 22 Oct 2021 04:22:47 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A60089F4F for ; Fri, 22 Oct 2021 04:22:46 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10144"; a="315424501" X-IronPort-AV: E=Sophos;i="5.87,171,1631602800"; d="scan'208";a="315424501" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2021 21:22:34 -0700 X-IronPort-AV: E=Sophos;i="5.87,171,1631602800"; d="scan'208";a="492249957" Received: from cooperch-ml.itwn.intel.com ([10.5.230.142]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2021 21:22:32 -0700 From: Cooper Chiou To: intel-gfx@lists.freedesktop.org Cc: Cooper Chiou , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Rodrigo Vivi , Jani Nikula , Chris Wilson , Tvrtko Ursulin , William Tseng , Shawn C Lee , Pawel Wilma Date: Fri, 22 Oct 2021 12:14:51 +0800 Message-Id: <20211022041451.27554-1-cooper.chiou@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20200916180745.627-1-cooper.chiou@intel.com> References: <20200916180745.627-1-cooper.chiou@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v7] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku for ChromiumOS projects. This system hang issue can be reproduced on Khronos OpenCL conformance tests by test_basic as well, and issue can be resolved by this patch on Linux. Slice specific MMIO read inaccurate so MGSR needs to be programmed appropriately to get correct reads from these slicet-related MMIOs. It dictates that before any MMIO read into Slice/Subslice specific registers, MCR packet control register(0xFDC) needs to be programmed to point to any enabled slice/subslice pair, especially GT1 fused sku since this issue can be reproduced on VP8 hardware encoding via ffmpeg on ChromiumOS devices. When exit PC7, MGSR will reset so that we have to skip fused subslice ID. Reference: HSD#1508045018,1405586840, BSID#0575 Cc: Ville Syrjälä Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Chris Wilson Cc: Tvrtko Ursulin Cc: William Tseng Cc: Shawn C Lee Cc: Pawel Wilma Signed-off-by: Cooper Chiou Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 41 +++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e1f362530889..8ae24da601b0 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -877,11 +877,52 @@ hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); } +static void +gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) +{ + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; + unsigned int slice, subslice; + u32 mcr, mcr_mask; + + GEM_BUG_ON(GRAPHICS_VER(i915) != 9); + + /* + * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml + * Before any MMIO read into slice/subslice specific registers, MCR + * packet control register needs to be programmed to point to any + * enabled s/ss pair. Otherwise, incorrect values will be returned. + * This means each subsequent MMIO read will be forwarded to an + * specific s/ss combination, but this is OK since these registers + * are consistent across s/ss in almost all cases. In the rare + * occasions, such as INSTDONE, where this value is dependent + * on s/ss combo, the read should be done with read_subslice_reg. + */ + slice = ffs(sseu->slice_mask) - 1; + GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); + subslice = ffs(intel_sseu_get_subslices(sseu, slice)); + GEM_BUG_ON(!subslice); + subslice--; + + /* + * We use GEN8_MCR..() macros to calculate the |mcr| value for + * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads + */ + mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; + + drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); + + wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); +} + static void gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; + /* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */ + gen9_wa_init_mcr(i915, wal); + /* WaDisableKillLogic:bxt,skl,kbl */ if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915)) wa_write_or(wal,