diff mbox series

[v4,2/3] drm/i915: Clean up GEN6 page valid macros

Message ID 20211111004549.144706-3-michael.cheng@intel.com (mailing list archive)
State New, archived
Headers show
Series Introduce new i915 macros for checking PTEs | expand

Commit Message

Michael Cheng Nov. 11, 2021, 12:45 a.m. UTC 
GEN6_PTE_VALID and GEN6_PDE_VALID both checks the 0 bit
to see weather the mapping of the corresponding graphics
memory page is valid. Instead of having two different
macros doing the same thing, this patch replaces the macros
with I915_PAGE_PRESENT.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/gen6_ppgtt.c |  2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +++++-----
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  2 --
 3 files changed, 6 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index ae693bf88ef0..aeefe70a0e83 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -19,7 +19,7 @@  static void gen6_write_pde(const struct gen6_ppgtt *ppgtt,
 	dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]);
 
 	/* Caller needs to make sure the write completes if necessary */
-	iowrite32(GEN6_PDE_ADDR_ENCODE(addr) | GEN6_PDE_VALID,
+	iowrite32(GEN6_PDE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT,
 		  ppgtt->pd_addr + pde);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 3f8e1ee0fbfa..995a1c47cd35 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -979,7 +979,7 @@  static u64 snb_pte_encode(dma_addr_t addr,
 			  enum i915_cache_level level,
 			  u32 flags)
 {
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT;
 
 	switch (level) {
 	case I915_CACHE_L3_LLC:
@@ -1000,7 +1000,7 @@  static u64 ivb_pte_encode(dma_addr_t addr,
 			  enum i915_cache_level level,
 			  u32 flags)
 {
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT;
 
 	switch (level) {
 	case I915_CACHE_L3_LLC:
@@ -1023,7 +1023,7 @@  static u64 byt_pte_encode(dma_addr_t addr,
 			  enum i915_cache_level level,
 			  u32 flags)
 {
-	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+	gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT;
 
 	if (!(flags & PTE_READ_ONLY))
 		pte |= BYT_PTE_WRITEABLE;
@@ -1038,7 +1038,7 @@  static u64 hsw_pte_encode(dma_addr_t addr,
 			  enum i915_cache_level level,
 			  u32 flags)
 {
-	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT;
 
 	if (level != I915_CACHE_NONE)
 		pte |= HSW_WB_LLC_AGE3;
@@ -1050,7 +1050,7 @@  static u64 iris_pte_encode(dma_addr_t addr,
 			   enum i915_cache_level level,
 			   u32 flags)
 {
-	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
+	gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT;
 
 	switch (level) {
 	case I915_CACHE_NONE:
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index fba9c0c18f4a..884bc250260c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -74,13 +74,11 @@  typedef u64 gen8_pte_t;
 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 #define GEN6_PTE_CACHE_LLC		(2 << 1)
 #define GEN6_PTE_UNCACHED		(1 << 1)
-#define GEN6_PTE_VALID			REG_BIT(0)
 
 #define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
 #define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
 #define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
 #define GEN6_PDE_SHIFT			22
-#define GEN6_PDE_VALID			REG_BIT(0)
 #define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))
 
 #define GEN7_PTE_CACHE_L3_LLC		(3 << 1)