| Message ID | 20211111004549.144706-4-michael.cheng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce new i915 macros for checking PTEs | expand |
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 995a1c47cd35..ac4ad82fdcdd 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -1026,7 +1026,7 @@ static u64 byt_pte_encode(dma_addr_t addr, gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | I915_PAGE_PRESENT; if (!(flags & PTE_READ_ONLY)) - pte |= BYT_PTE_WRITEABLE; + pte |= I915_PAGE_RW; if (level != I915_CACHE_NONE) pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 884bc250260c..0eb77e2fb45f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -84,7 +84,6 @@ typedef u64 gen8_pte_t; #define GEN7_PTE_CACHE_L3_LLC (3 << 1) #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2) -#define BYT_PTE_WRITEABLE REG_BIT(1) #define GEN12_PPGTT_PTE_LM BIT_ULL(11)
Removes BYT_PTE_WRITEABLE and replace it with I915_PAGE_RW. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-)