From patchwork Wed Nov 17 22:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinay Belgaumkar X-Patchwork-Id: 12625711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70525C433EF for ; Wed, 17 Nov 2021 22:50:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BEFA6101C for ; Wed, 17 Nov 2021 22:50:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3BEFA6101C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80D7B6E283; Wed, 17 Nov 2021 22:50:23 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 896C06E283; Wed, 17 Nov 2021 22:50:22 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10171"; a="221285254" X-IronPort-AV: E=Sophos;i="5.87,243,1631602800"; d="scan'208";a="221285254" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2021 14:50:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,243,1631602800"; d="scan'208";a="536467626" Received: from vbelgaum-ubuntu.fm.intel.com ([10.1.27.27]) by orsmga001.jf.intel.com with ESMTP; 17 Nov 2021 14:50:21 -0800 From: Vinay Belgaumkar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Wed, 17 Nov 2021 14:49:53 -0800 Message-Id: <20211117224955.28999-2-vinay.belgaumkar@intel.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211117224955.28999-1-vinay.belgaumkar@intel.com> References: <20211117224955.28999-1-vinay.belgaumkar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Spread virtual engines over idle engines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Chris Wilson Everytime we come to the end of a virtual engine's context, re-randomise it's siblings[]. As we schedule the siblings' tasklets in the order they are in the array, earlier entries are executed first (when idle) and so will be preferred when scheduling the next virtual request. Currently, we only update the array when switching onto a new idle engine, so we prefer to stick on the last execute engine, keeping the work compact. However, it can be beneficial to spread the work out across idle engines, so choose another sibling as our preferred target at the end of the context's execution. Signed-off-by: Chris Wilson Cc: Vinay Belgaumkar Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin Acked-by: Rodrigo Vivi --- .../drm/i915/gt/intel_execlists_submission.c | 80 ++++++++++++------- 1 file changed, 52 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index ca03880fa7e4..b95bbc8fb91a 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -539,6 +539,41 @@ static void execlists_schedule_in(struct i915_request *rq, int idx) GEM_BUG_ON(intel_context_inflight(ce) != rq->engine); } +static void virtual_xfer_context(struct virtual_engine *ve, + struct intel_engine_cs *engine) +{ + unsigned int n; + + if (likely(engine == ve->siblings[0])) + return; + + if (!intel_engine_has_relative_mmio(engine)) + lrc_update_offsets(&ve->context, engine); + + /* + * Move the bound engine to the top of the list for + * future execution. We then kick this tasklet first + * before checking others, so that we preferentially + * reuse this set of bound registers. + */ + for (n = 1; n < ve->num_siblings; n++) { + if (ve->siblings[n] == engine) { + swap(ve->siblings[n], ve->siblings[0]); + break; + } + } +} + +static int ve_random_sibling(struct virtual_engine *ve) +{ + return prandom_u32_max(ve->num_siblings); +} + +static int ve_random_other_sibling(struct virtual_engine *ve) +{ + return 1 + prandom_u32_max(ve->num_siblings - 1); +} + static void resubmit_virtual_request(struct i915_request *rq, struct virtual_engine *ve) { @@ -578,8 +613,23 @@ static void kick_siblings(struct i915_request *rq, struct intel_context *ce) rq->execution_mask != engine->mask) resubmit_virtual_request(rq, ve); - if (READ_ONCE(ve->request)) + /* + * Reschedule with a new "preferred" sibling. + * + * The tasklets are executed in the order of ve->siblings[], so + * siblings[0] receives preferrential treatment of greedily checking + * for execution of the virtual engine. At this point, the virtual + * engine is no longer in the current GPU cache due to idleness or + * contention, so it can be executed on any without penalty. We + * re-randomise at this point in order to spread light loads across + * the system, heavy overlapping loads will continue to be greedily + * executed by the first available engine. + */ + if (READ_ONCE(ve->request)) { + virtual_xfer_context(ve, + ve->siblings[ve_random_other_sibling(ve)]); tasklet_hi_schedule(&ve->base.sched_engine->tasklet); + } } static void __execlists_schedule_out(struct i915_request * const rq, @@ -1030,32 +1080,6 @@ first_virtual_engine(struct intel_engine_cs *engine) return NULL; } -static void virtual_xfer_context(struct virtual_engine *ve, - struct intel_engine_cs *engine) -{ - unsigned int n; - - if (likely(engine == ve->siblings[0])) - return; - - GEM_BUG_ON(READ_ONCE(ve->context.inflight)); - if (!intel_engine_has_relative_mmio(engine)) - lrc_update_offsets(&ve->context, engine); - - /* - * Move the bound engine to the top of the list for - * future execution. We then kick this tasklet first - * before checking others, so that we preferentially - * reuse this set of bound registers. - */ - for (n = 1; n < ve->num_siblings; n++) { - if (ve->siblings[n] == engine) { - swap(ve->siblings[n], ve->siblings[0]); - break; - } - } -} - static void defer_request(struct i915_request *rq, struct list_head * const pl) { LIST_HEAD(list); @@ -3590,7 +3614,7 @@ static void virtual_engine_initial_hint(struct virtual_engine *ve) * NB This does not force us to execute on this engine, it will just * typically be the first we inspect for submission. */ - swp = prandom_u32_max(ve->num_siblings); + swp = ve_random_sibling(ve); if (swp) swap(ve->siblings[swp], ve->siblings[0]); }