diff mbox series

drm/i915: Reject 5k on HDR planes for planar fb formats

Message ID 20211118062516.22535-1-vidya.srinivas@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Reject 5k on HDR planes for planar fb formats | expand

Commit Message

Srinivas, Vidya Nov. 18, 2021, 6:25 a.m. UTC
PLANE_CUS_CTL has a restriction of 4096 width even though
PLANE_SIZE and scaler size registers supports max 5120.
Reject 5k on HDR plane for planar formats like NV12
to let the user space know about it.

Without this patch, when 5k content is sent on HDR plane
with NV12 content, FIFO underrun is seen and screen blanks
out. Issue is seen on both TGL and ADL platforms.

Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Yashashvi Shantam <shantam.yashashvi@intel.com>
---
 drivers/gpu/drm/i915/display/skl_scaler.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Ville Syrjala Nov. 30, 2021, 9:30 a.m. UTC | #1
On Thu, Nov 18, 2021 at 11:55:16AM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Reject 5k on HDR plane for planar formats like NV12
> to let the user space know about it.
> 
> Without this patch, when 5k content is sent on HDR plane
> with NV12 content, FIFO underrun is seen and screen blanks
> out. Issue is seen on both TGL and ADL platforms.
> 
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> Signed-off-by: Yashashvi Shantam <shantam.yashashvi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_scaler.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 37eabeff8197..e2e52f5dca3b 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -86,6 +86,7 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
>  #define ICL_MAX_DST_H 4096
>  #define SKL_MIN_YUV_420_SRC_W 16
>  #define SKL_MIN_YUV_420_SRC_H 16
> +#define MAX_CUSCTL_W 4096
>  
>  static int
>  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> @@ -221,6 +222,14 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	bool force_detach = !fb || !plane_state->uapi.visible;
>  	bool need_scaler = false;
>  
> +	/* PLANE_CUS_CTL size max 4096 */
> +	if (icl_is_hdr_plane(dev_priv, intel_plane->id) &&
> +	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
> +	    (drm_rect_width(&plane_state->uapi.src) >> 16) > MAX_CUSCTL_W) {
> +		DRM_ERROR("HDR chroma upsampler size exceeds limits\n");
> +		return -EINVAL;
> +	}

Wrong place. Should go into the plane->max_width() hook. There also
seems to be a minimum height requirement for the CUS which we're not
checking either.

> +
>  	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
>  	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
>  	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> -- 
> 2.33.0
Srinivas, Vidya Nov. 30, 2021, 4:20 p.m. UTC | #2
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, November 30, 2021 3:01 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
> <shantam.yashashvi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Reject 5k on HDR planes for planar
> fb formats
> 
> On Thu, Nov 18, 2021 at 11:55:16AM +0530, Vidya Srinivas wrote:
> > PLANE_CUS_CTL has a restriction of 4096 width even though PLANE_SIZE
> > and scaler size registers supports max 5120.
> > Reject 5k on HDR plane for planar formats like NV12 to let the user
> > space know about it.
> >
> > Without this patch, when 5k content is sent on HDR plane with NV12
> > content, FIFO underrun is seen and screen blanks out. Issue is seen on
> > both TGL and ADL platforms.
> >
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > Signed-off-by: Yashashvi Shantam <shantam.yashashvi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/skl_scaler.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
> > b/drivers/gpu/drm/i915/display/skl_scaler.c
> > index 37eabeff8197..e2e52f5dca3b 100644
> > --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> > @@ -86,6 +86,7 @@ static u16 skl_scaler_calc_phase(int sub, int scale,
> > bool chroma_cosited)  #define ICL_MAX_DST_H 4096  #define
> > SKL_MIN_YUV_420_SRC_W 16  #define SKL_MIN_YUV_420_SRC_H 16
> > +#define MAX_CUSCTL_W 4096
> >
> >  static int
> >  skl_update_scaler(struct intel_crtc_state *crtc_state, bool
> > force_detach, @@ -221,6 +222,14 @@ int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> >  	bool force_detach = !fb || !plane_state->uapi.visible;
> >  	bool need_scaler = false;
> >
> > +	/* PLANE_CUS_CTL size max 4096 */
> > +	if (icl_is_hdr_plane(dev_priv, intel_plane->id) &&
> > +	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier) &&
> > +	    (drm_rect_width(&plane_state->uapi.src) >> 16) >
> MAX_CUSCTL_W) {
> > +		DRM_ERROR("HDR chroma upsampler size exceeds
> limits\n");
> > +		return -EINVAL;
> > +	}
> 
> Wrong place. Should go into the plane->max_width() hook. There also seems
> to be a minimum height requirement for the CUS which we're not checking
> either.
> 
Thank you very much Ville for the patch review. Have moved the check to max_width.
Minimum horizontal should be 8 and vertical should be 4 - Haven't added in this yet.
Can you kindly have a check please https://patchwork.freedesktop.org/patch/464727/

Regards
Vidya

> > +
> >  	/* Pre-gen11 and SDR planes always need a scaler for planar
> formats. */
> >  	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
> >  	    fb && intel_format_info_is_yuv_semiplanar(fb->format,
> > fb->modifier))
> > --
> > 2.33.0
> 
> --
> Ville Syrjälä
> Intel
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 37eabeff8197..e2e52f5dca3b 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -86,6 +86,7 @@  static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
 #define ICL_MAX_DST_H 4096
 #define SKL_MIN_YUV_420_SRC_W 16
 #define SKL_MIN_YUV_420_SRC_H 16
+#define MAX_CUSCTL_W 4096
 
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
@@ -221,6 +222,14 @@  int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	bool force_detach = !fb || !plane_state->uapi.visible;
 	bool need_scaler = false;
 
+	/* PLANE_CUS_CTL size max 4096 */
+	if (icl_is_hdr_plane(dev_priv, intel_plane->id) &&
+	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
+	    (drm_rect_width(&plane_state->uapi.src) >> 16) > MAX_CUSCTL_W) {
+		DRM_ERROR("HDR chroma upsampler size exceeds limits\n");
+		return -EINVAL;
+	}
+
 	/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
 	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
 	    fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))