| Message ID | 20211123144559.3474989-1-ravitejax.goud.talla@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() | expand |
Hi Harrison, This patch will fix guc enabling error which is tested on local setup, please make your comments. Thanks, Raviteja -----Original Message----- From: Talla, RavitejaX Goud <ravitejax.goud.talla@intel.com> Sent: Tuesday, November 23, 2021 8:16 PM To: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>; Harrison, John C <john.c.harrison@intel.com> Cc: Talla, RavitejaX Goud <ravitejax.goud.talla@intel.com> Subject: [PATCH] drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() From: raviteja goud talla <ravitejax.goud.talla@intel.com> Bspec page says "Reset: BUS", Accordingly moving w/a's: Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init() Which will resolve guc enabling error Cc: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: raviteja goud talla <ravitejax.goud.talla@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a9727447c037..4f7b598d21b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1231,6 +1231,15 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* Wa_1407352427:icl,ehl */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); + + /* Wa_1406680159:icl,ehl */ + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE, + GWUNIT_CLKGATE_DIS); + /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) @@ -2272,15 +2281,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* Wa_1407352427:icl,ehl */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - PSDUNIT_CLKGATE_DIS); - - /* Wa_1406680159:icl,ehl */ - wa_write_or(wal, - SUBSLICE_UNIT_LEVEL_CLKGATE, - GWUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0] -- 2.30.2
On 11/23/2021 06:45, ravitejax.goud.talla@intel.com wrote: > From: raviteja goud talla <ravitejax.goud.talla@intel.com> > > Bspec page says "Reset: BUS", Accordingly moving w/a's: > Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init() > Which will resolve guc enabling error > > Cc: John Harrison <John.C.Harrison@Intel.com> > Signed-off-by: raviteja goud talla <ravitejax.goud.talla@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index a9727447c037..4f7b598d21b1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1231,6 +1231,15 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > GAMT_CHKN_BIT_REG, > GAMT_CHKN_DISABLE_L3_COH_PIPE); > > + /* Wa_1407352427:icl,ehl */ > + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > + PSDUNIT_CLKGATE_DIS); > + > + /* Wa_1406680159:icl,ehl */ > + wa_write_or(wal, > + SUBSLICE_UNIT_LEVEL_CLKGATE, > + GWUNIT_CLKGATE_DIS); > + > /* Wa_1607087056:icl,ehl,jsl */ > if (IS_ICELAKE(i915) || > IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) > @@ -2272,15 +2281,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, > VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); > > - /* Wa_1407352427:icl,ehl */ > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, > - PSDUNIT_CLKGATE_DIS); > - > - /* Wa_1406680159:icl,ehl */ > - wa_write_or(wal, > - SUBSLICE_UNIT_LEVEL_CLKGATE, > - GWUNIT_CLKGATE_DIS); > - > /* > * Wa_1408767742:icl[a2..forever],ehl[all] > * Wa_1605460711:icl[a0..c0]
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index a9727447c037..4f7b598d21b1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1231,6 +1231,15 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* Wa_1407352427:icl,ehl */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); + + /* Wa_1406680159:icl,ehl */ + wa_write_or(wal, + SUBSLICE_UNIT_LEVEL_CLKGATE, + GWUNIT_CLKGATE_DIS); + /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) @@ -2272,15 +2281,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* Wa_1407352427:icl,ehl */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, - PSDUNIT_CLKGATE_DIS); - - /* Wa_1406680159:icl,ehl */ - wa_write_or(wal, - SUBSLICE_UNIT_LEVEL_CLKGATE, - GWUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0]