[02/14] drm/i915: Rename plane YUV order bits

Message ID	20211201152552.7821-3-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Dec 2021 17:25:40 +0200 Message-Id: <20211201152552.7821-3-ville.syrjala@linux.intel.com> In-Reply-To: <20211201152552.7821-1-ville.syrjala@linux.intel.com> References: <20211201152552.7821-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: Plane register cleanup \| expand [00/14] drm/i915: Plane register cleanup [01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio [02/14] drm/i915: Rename plane YUV order bits [03/14] drm/i915: Get rid of the "sizes are 0 based" stuff [04/14] drm/i915: Sipmplify PLANE_STRIDE masking [05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits [06/14] drm/i915: Use REG_BIT() & co. for universal plane bits [07/14] drm/i915: Clean up pre-skl primary plane registers [08/14] drm/i915: Clean up ivb+ sprite plane registers [09/14] drm/i915: Clean up vlv/chv sprite plane registers [10/14] drm/i915: Clean up g4x+ sprite plane registers [11/14] drm/i915: Clean up cursor registers [12/14] drm/i915: Extract skl_plane_aux_dist() [13/14] drm/i915: Declutter color key register stuff [14/14] drm/i915: Nuke pointless middle men for skl+ plane programming

Message ID

20211201152552.7821-3-ville.syrjala@linux.intel.com (mailing list archive)

State

New, archived

Headers

From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Wed,  1 Dec 2021 17:25:40 +0200
Message-Id: <20211201152552.7821-3-ville.syrjala@linux.intel.com>
In-Reply-To: <20211201152552.7821-1-ville.syrjala@linux.intel.com>
References: <20211201152552.7821-1-ville.syrjala@linux.intel.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Subject: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
Precedence: list
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Series

drm/i915: Plane register cleanup | expand

Commit Message

Ville Syrjälä Dec. 1, 2021, 3:25 p.m. UTC

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename the YUV byte order bits to be a bit more consistent.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c |  8 ++++----
 drivers/gpu/drm/i915/i915_reg.h                    | 14 +++++++-------
 2 files changed, 11 insertions(+), 11 deletions(-)

Comments

Souza, Jose Dec. 1, 2021, 5:14 p.m. UTC | #1

On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rename the YUV byte order bits to be a bit more consistent.

Why rename bits not used? Would be better already nuke it.
Anyways up to you.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c |  8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h                    | 14 +++++++-------
>  2 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 845b99844ec6..9ff24a0e79b4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>  	case DRM_FORMAT_XYUV8888:
>  		return PLANE_CTL_FORMAT_XYUV;
>  	case DRM_FORMAT_YUYV:
> -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
>  	case DRM_FORMAT_YVYU:
> -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
>  	case DRM_FORMAT_UYVY:
> -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
>  	case DRM_FORMAT_VYUY:
> -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
>  	case DRM_FORMAT_NV12:
>  		return PLANE_CTL_FORMAT_NV12;
>  	case DRM_FORMAT_P010:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c0471f20e53..02d8db03c0bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6966,7 +6966,7 @@ enum {
>  #define   DVS_SOURCE_KEY	(1 << 22)
>  #define   DVS_RGB_ORDER_XBGR	(1 << 20)
>  #define   DVS_YUV_FORMAT_BT709	(1 << 18)
> -#define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define   DVS_YUV_ORDER_MASK	(3 << 16)
>  #define   DVS_YUV_ORDER_YUYV	(0 << 16)
>  #define   DVS_YUV_ORDER_UYVY	(1 << 16)
>  #define   DVS_YUV_ORDER_YVYU	(2 << 16)
> @@ -7045,7 +7045,7 @@ enum {
>  #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
>  #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
>  #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
> -#define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
> +#define   SPRITE_YUV_ORDER_MASK		(3 << 16)
>  #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
>  #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
>  #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
> @@ -7130,7 +7130,7 @@ enum {
>  #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
>  #define   SP_SOURCE_KEY			(1 << 22)
>  #define   SP_YUV_FORMAT_BT709		(1 << 18)
> -#define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
> +#define   SP_YUV_ORDER_MASK		(3 << 16)
>  #define   SP_YUV_ORDER_YUYV		(0 << 16)
>  #define   SP_YUV_ORDER_UYVY		(1 << 16)
>  #define   SP_YUV_ORDER_YVYU		(2 << 16)
> @@ -7271,10 +7271,10 @@ enum {
>  #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
>  #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
>  #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
> -#define   PLANE_CTL_YUV422_YUYV			(0 << 16)
> -#define   PLANE_CTL_YUV422_UYVY			(1 << 16)
> -#define   PLANE_CTL_YUV422_YVYU			(2 << 16)
> -#define   PLANE_CTL_YUV422_VYUY			(3 << 16)
> +#define   PLANE_CTL_YUV422_ORDER_YUYV		(0 << 16)
> +#define   PLANE_CTL_YUV422_ORDER_UYVY		(1 << 16)
> +#define   PLANE_CTL_YUV422_ORDER_YVYU		(2 << 16)
> +#define   PLANE_CTL_YUV422_ORDER_VYUY		(3 << 16)
>  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
>  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
>  #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */

Ville Syrjälä Dec. 2, 2021, 11:53 a.m. UTC | #2

On Wed, Dec 01, 2021 at 05:14:39PM +0000, Souza, Jose wrote:
> On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Rename the YUV byte order bits to be a bit more consistent.
> 
> Why rename bits not used? Would be better already nuke it.
> Anyways up to you.

We'll need the masks for the REG_FIELD_PREP() stuff later.

> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c |  8 ++++----
> >  drivers/gpu/drm/i915/i915_reg.h                    | 14 +++++++-------
> >  2 files changed, 11 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 845b99844ec6..9ff24a0e79b4 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> >  	case DRM_FORMAT_XYUV8888:
> >  		return PLANE_CTL_FORMAT_XYUV;
> >  	case DRM_FORMAT_YUYV:
> > -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> > +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> >  	case DRM_FORMAT_YVYU:
> > -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> > +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> >  	case DRM_FORMAT_UYVY:
> > -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> > +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> >  	case DRM_FORMAT_VYUY:
> > -		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> > +		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> >  	case DRM_FORMAT_NV12:
> >  		return PLANE_CTL_FORMAT_NV12;
> >  	case DRM_FORMAT_P010:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3c0471f20e53..02d8db03c0bf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6966,7 +6966,7 @@ enum {
> >  #define   DVS_SOURCE_KEY	(1 << 22)
> >  #define   DVS_RGB_ORDER_XBGR	(1 << 20)
> >  #define   DVS_YUV_FORMAT_BT709	(1 << 18)
> > -#define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> > +#define   DVS_YUV_ORDER_MASK	(3 << 16)
> >  #define   DVS_YUV_ORDER_YUYV	(0 << 16)
> >  #define   DVS_YUV_ORDER_UYVY	(1 << 16)
> >  #define   DVS_YUV_ORDER_YVYU	(2 << 16)
> > @@ -7045,7 +7045,7 @@ enum {
> >  #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
> >  #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
> >  #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
> > -#define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
> > +#define   SPRITE_YUV_ORDER_MASK		(3 << 16)
> >  #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
> >  #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
> >  #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
> > @@ -7130,7 +7130,7 @@ enum {
> >  #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
> >  #define   SP_SOURCE_KEY			(1 << 22)
> >  #define   SP_YUV_FORMAT_BT709		(1 << 18)
> > -#define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
> > +#define   SP_YUV_ORDER_MASK		(3 << 16)
> >  #define   SP_YUV_ORDER_YUYV		(0 << 16)
> >  #define   SP_YUV_ORDER_UYVY		(1 << 16)
> >  #define   SP_YUV_ORDER_YVYU		(2 << 16)
> > @@ -7271,10 +7271,10 @@ enum {
> >  #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
> >  #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
> >  #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
> > -#define   PLANE_CTL_YUV422_YUYV			(0 << 16)
> > -#define   PLANE_CTL_YUV422_UYVY			(1 << 16)
> > -#define   PLANE_CTL_YUV422_YVYU			(2 << 16)
> > -#define   PLANE_CTL_YUV422_VYUY			(3 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_YUYV		(0 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_UYVY		(1 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_YVYU		(2 << 16)
> > +#define   PLANE_CTL_YUV422_ORDER_VYUY		(3 << 16)
> >  #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
> >  #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */
>

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 845b99844ec6..9ff24a0e79b4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -672,13 +672,13 @@  static u32 skl_plane_ctl_format(u32 pixel_format)
 	case DRM_FORMAT_XYUV8888:
 		return PLANE_CTL_FORMAT_XYUV;
 	case DRM_FORMAT_YUYV:
-		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
+		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
 	case DRM_FORMAT_YVYU:
-		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
+		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
 	case DRM_FORMAT_UYVY:
-		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
+		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
 	case DRM_FORMAT_VYUY:
-		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
 	case DRM_FORMAT_P010:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c0471f20e53..02d8db03c0bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6966,7 +6966,7 @@  enum {
 #define   DVS_SOURCE_KEY	(1 << 22)
 #define   DVS_RGB_ORDER_XBGR	(1 << 20)
 #define   DVS_YUV_FORMAT_BT709	(1 << 18)
-#define   DVS_YUV_BYTE_ORDER_MASK (3 << 16)
+#define   DVS_YUV_ORDER_MASK	(3 << 16)
 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
 #define   DVS_YUV_ORDER_UYVY	(1 << 16)
 #define   DVS_YUV_ORDER_YVYU	(2 << 16)
@@ -7045,7 +7045,7 @@  enum {
 #define   SPRITE_RGB_ORDER_RGBX		(1 << 20) /* only for 888 and 161616 */
 #define   SPRITE_YUV_TO_RGB_CSC_DISABLE	(1 << 19)
 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
-#define   SPRITE_YUV_BYTE_ORDER_MASK	(3 << 16)
+#define   SPRITE_YUV_ORDER_MASK		(3 << 16)
 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
 #define   SPRITE_YUV_ORDER_UYVY		(1 << 16)
 #define   SPRITE_YUV_ORDER_YVYU		(2 << 16)
@@ -7130,7 +7130,7 @@  enum {
 #define   SP_ALPHA_PREMULTIPLY		(1 << 23) /* CHV pipe B */
 #define   SP_SOURCE_KEY			(1 << 22)
 #define   SP_YUV_FORMAT_BT709		(1 << 18)
-#define   SP_YUV_BYTE_ORDER_MASK	(3 << 16)
+#define   SP_YUV_ORDER_MASK		(3 << 16)
 #define   SP_YUV_ORDER_YUYV		(0 << 16)
 #define   SP_YUV_ORDER_UYVY		(1 << 16)
 #define   SP_YUV_ORDER_YVYU		(2 << 16)
@@ -7271,10 +7271,10 @@  enum {
 #define   PLANE_CTL_YUV420_Y_PLANE		(1 << 19)
 #define   PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18)
 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
-#define   PLANE_CTL_YUV422_YUYV			(0 << 16)
-#define   PLANE_CTL_YUV422_UYVY			(1 << 16)
-#define   PLANE_CTL_YUV422_YVYU			(2 << 16)
-#define   PLANE_CTL_YUV422_VYUY			(3 << 16)
+#define   PLANE_CTL_YUV422_ORDER_YUYV		(0 << 16)
+#define   PLANE_CTL_YUV422_ORDER_UYVY		(1 << 16)
+#define   PLANE_CTL_YUV422_ORDER_YVYU		(2 << 16)
+#define   PLANE_CTL_YUV422_ORDER_VYUY		(3 << 16)
 #define   PLANE_CTL_RENDER_DECOMPRESSION_ENABLE	(1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE	(1 << 14)
 #define   PLANE_CTL_CLEAR_COLOR_DISABLE		(1 << 13) /* TGL+ */

[02/14] drm/i915: Rename plane YUV order bits

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