| Message ID | 20220110234520.6836-1-clinton.a.taylor@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/snps: vswing value refined for SNPS phys | expand |
On Mon, 10 Jan 2022, clinton.a.taylor@intel.com wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > Updated new values from BSPEC. > > BSPEC: 53920 > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 42 +++++++++---------- > 1 file changed, 21 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 1e689d573512..09d6ab13536c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { > }; > > static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { > - { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ > - { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ > - { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ > - { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ > - { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ > - { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ > - { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ > - { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ > - { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ > + { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */ > + { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */ > + { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */ > + { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */ > + { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */ > + { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */ > + { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */ > + { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */ > + { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */ > { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ > }; > > @@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans = { > > static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { > { .snps = { 62, 0, 0 } }, /* preset 0 */ > - { .snps = { 56, 0, 6 } }, /* preset 1 */ > - { .snps = { 51, 0, 11 } }, /* preset 2 */ > - { .snps = { 48, 0, 14 } }, /* preset 3 */ > - { .snps = { 43, 0, 19 } }, /* preset 4 */ > + { .snps = { 55, 0, 7 } }, /* preset 1 */ > + { .snps = { 50, 0, 12 } }, /* preset 2 */ > + { .snps = { 44, 0, 18 } }, /* preset 3 */ > + { .snps = { 35, 0, 21 } }, /* preset 4 */ > { .snps = { 59, 3, 0 } }, /* preset 5 */ > { .snps = { 53, 3, 6 } }, /* preset 6 */ > - { .snps = { 49, 3, 10 } }, /* preset 7 */ > - { .snps = { 45, 3, 14 } }, /* preset 8 */ > - { .snps = { 42, 3, 17 } }, /* preset 9 */ > + { .snps = { 48, 3, 11 } }, /* preset 7 */ > + { .snps = { 42, 5, 15 } }, /* preset 8 */ > + { .snps = { 37, 5, 20 } }, /* preset 9 */ > { .snps = { 56, 6, 0 } }, /* preset 10 */ > - { .snps = { 50, 6, 6 } }, /* preset 11 */ > - { .snps = { 47, 6, 9 } }, /* preset 12 */ > - { .snps = { 42, 6, 14 } }, /* preset 13 */ > - { .snps = { 46, 8, 8 } }, /* preset 14 */ > - { .snps = { 56, 3, 3 } }, /* preset 15 */ > + { .snps = { 48, 7, 7 } }, /* preset 11 */ > + { .snps = { 45, 7, 10 } }, /* preset 12 */ > + { .snps = { 39, 8, 15 } }, /* preset 13 */ > + { .snps = { 48, 14, 0 } }, /* preset 14 */ > + { .snps = { 45, 4, 4 } }, /* preset 15 */ > }; > > static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
On Mon, 2022-01-10 at 15:45 -0800, clinton.a.taylor@intel.com wrote: > From: Clint Taylor <clinton.a.taylor@intel.com> > > Updated new values from BSPEC. > > BSPEC: 53920 > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 42 +++++++++---------- > 1 file changed, 21 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 1e689d573512..09d6ab13536c 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { > }; > > static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { > - { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ > - { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ > - { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ > - { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ > - { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ > - { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ > - { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ > - { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ > - { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ > + { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */ > + { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */ > + { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */ > + { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */ > + { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */ > + { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */ > + { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */ > + { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */ > + { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */ > { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ > }; > > @@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans = { > > static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { > { .snps = { 62, 0, 0 } }, /* preset 0 */ > - { .snps = { 56, 0, 6 } }, /* preset 1 */ > - { .snps = { 51, 0, 11 } }, /* preset 2 */ > - { .snps = { 48, 0, 14 } }, /* preset 3 */ > - { .snps = { 43, 0, 19 } }, /* preset 4 */ > + { .snps = { 55, 0, 7 } }, /* preset 1 */ > + { .snps = { 50, 0, 12 } }, /* preset 2 */ > + { .snps = { 44, 0, 18 } }, /* preset 3 */ > + { .snps = { 35, 0, 21 } }, /* preset 4 */ > { .snps = { 59, 3, 0 } }, /* preset 5 */ > { .snps = { 53, 3, 6 } }, /* preset 6 */ > - { .snps = { 49, 3, 10 } }, /* preset 7 */ > - { .snps = { 45, 3, 14 } }, /* preset 8 */ > - { .snps = { 42, 3, 17 } }, /* preset 9 */ > + { .snps = { 48, 3, 11 } }, /* preset 7 */ > + { .snps = { 42, 5, 15 } }, /* preset 8 */ > + { .snps = { 37, 5, 20 } }, /* preset 9 */ > { .snps = { 56, 6, 0 } }, /* preset 10 */ > - { .snps = { 50, 6, 6 } }, /* preset 11 */ > - { .snps = { 47, 6, 9 } }, /* preset 12 */ > - { .snps = { 42, 6, 14 } }, /* preset 13 */ > - { .snps = { 46, 8, 8 } }, /* preset 14 */ > - { .snps = { 56, 3, 3 } }, /* preset 15 */ > + { .snps = { 48, 7, 7 } }, /* preset 11 */ > + { .snps = { 45, 7, 10 } }, /* preset 12 */ > + { .snps = { 39, 8, 15 } }, /* preset 13 */ > + { .snps = { 48, 14, 0 } }, /* preset 14 */ > + { .snps = { 45, 4, 4 } }, /* preset 15 */ > }; > > static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
On Tue, 11 Jan 2022, "Souza, Jose" <jose.souza@intel.com> wrote: > On Mon, 2022-01-10 at 15:45 -0800, clinton.a.taylor@intel.com wrote: >> From: Clint Taylor <clinton.a.taylor@intel.com> >> >> Updated new values from BSPEC. >> >> BSPEC: 53920 >> > > Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Oh, I failed to reply that I've pushed this already. But thanks for confirming it matches the spec. :) BR, Jani. > >> Cc: Jani Nikula <jani.nikula@intel.com> >> Cc: José Roberto de Souza <jose.souza@intel.com> >> Cc: Imre Deak <imre.deak@intel.com> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> >> --- >> .../drm/i915/display/intel_ddi_buf_trans.c | 42 +++++++++---------- >> 1 file changed, 21 insertions(+), 21 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> index 1e689d573512..09d6ab13536c 100644 >> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c >> @@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { >> }; >> >> static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { >> - { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ >> - { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ >> - { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ >> - { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ >> - { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ >> - { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ >> - { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ >> - { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ >> - { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ >> + { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */ >> + { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */ >> + { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */ >> + { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */ >> + { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */ >> + { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */ >> + { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */ >> + { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */ >> + { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */ >> { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ >> }; >> >> @@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans = { >> >> static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { >> { .snps = { 62, 0, 0 } }, /* preset 0 */ >> - { .snps = { 56, 0, 6 } }, /* preset 1 */ >> - { .snps = { 51, 0, 11 } }, /* preset 2 */ >> - { .snps = { 48, 0, 14 } }, /* preset 3 */ >> - { .snps = { 43, 0, 19 } }, /* preset 4 */ >> + { .snps = { 55, 0, 7 } }, /* preset 1 */ >> + { .snps = { 50, 0, 12 } }, /* preset 2 */ >> + { .snps = { 44, 0, 18 } }, /* preset 3 */ >> + { .snps = { 35, 0, 21 } }, /* preset 4 */ >> { .snps = { 59, 3, 0 } }, /* preset 5 */ >> { .snps = { 53, 3, 6 } }, /* preset 6 */ >> - { .snps = { 49, 3, 10 } }, /* preset 7 */ >> - { .snps = { 45, 3, 14 } }, /* preset 8 */ >> - { .snps = { 42, 3, 17 } }, /* preset 9 */ >> + { .snps = { 48, 3, 11 } }, /* preset 7 */ >> + { .snps = { 42, 5, 15 } }, /* preset 8 */ >> + { .snps = { 37, 5, 20 } }, /* preset 9 */ >> { .snps = { 56, 6, 0 } }, /* preset 10 */ >> - { .snps = { 50, 6, 6 } }, /* preset 11 */ >> - { .snps = { 47, 6, 9 } }, /* preset 12 */ >> - { .snps = { 42, 6, 14 } }, /* preset 13 */ >> - { .snps = { 46, 8, 8 } }, /* preset 14 */ >> - { .snps = { 56, 3, 3 } }, /* preset 15 */ >> + { .snps = { 48, 7, 7 } }, /* preset 11 */ >> + { .snps = { 45, 7, 10 } }, /* preset 12 */ >> + { .snps = { 39, 8, 15 } }, /* preset 13 */ >> + { .snps = { 48, 14, 0 } }, /* preset 14 */ >> + { .snps = { 45, 4, 4 } }, /* preset 15 */ >> }; >> >> static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = { >
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 1e689d573512..09d6ab13536c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -985,15 +985,15 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = { }; static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = { - { .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */ - { .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */ - { .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */ - { .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */ - { .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */ - { .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */ - { .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */ - { .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */ - { .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */ + { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */ + { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */ + { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */ + { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */ + { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */ + { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */ + { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */ + { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */ + { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */ { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */ }; @@ -1005,21 +1005,21 @@ static const struct intel_ddi_buf_trans dg2_snps_trans = { static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = { { .snps = { 62, 0, 0 } }, /* preset 0 */ - { .snps = { 56, 0, 6 } }, /* preset 1 */ - { .snps = { 51, 0, 11 } }, /* preset 2 */ - { .snps = { 48, 0, 14 } }, /* preset 3 */ - { .snps = { 43, 0, 19 } }, /* preset 4 */ + { .snps = { 55, 0, 7 } }, /* preset 1 */ + { .snps = { 50, 0, 12 } }, /* preset 2 */ + { .snps = { 44, 0, 18 } }, /* preset 3 */ + { .snps = { 35, 0, 21 } }, /* preset 4 */ { .snps = { 59, 3, 0 } }, /* preset 5 */ { .snps = { 53, 3, 6 } }, /* preset 6 */ - { .snps = { 49, 3, 10 } }, /* preset 7 */ - { .snps = { 45, 3, 14 } }, /* preset 8 */ - { .snps = { 42, 3, 17 } }, /* preset 9 */ + { .snps = { 48, 3, 11 } }, /* preset 7 */ + { .snps = { 42, 5, 15 } }, /* preset 8 */ + { .snps = { 37, 5, 20 } }, /* preset 9 */ { .snps = { 56, 6, 0 } }, /* preset 10 */ - { .snps = { 50, 6, 6 } }, /* preset 11 */ - { .snps = { 47, 6, 9 } }, /* preset 12 */ - { .snps = { 42, 6, 14 } }, /* preset 13 */ - { .snps = { 46, 8, 8 } }, /* preset 14 */ - { .snps = { 56, 3, 3 } }, /* preset 15 */ + { .snps = { 48, 7, 7 } }, /* preset 11 */ + { .snps = { 45, 7, 10 } }, /* preset 12 */ + { .snps = { 39, 8, 15 } }, /* preset 13 */ + { .snps = { 48, 14, 0 } }, /* preset 14 */ + { .snps = { 45, 4, 4 } }, /* preset 15 */ }; static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {