diff mbox series

[RFC,1/2] drm/i915: add new flag has_psr2_sel_fetch

Message ID 20220112140031.39823-2-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series Add has_psr2_sel_fech flag | expand

Commit Message

Hogander, Jouni Jan. 12, 2022, 2 p.m. UTC
This patch is adding new information into intel_device_info to see
whether i915 is psr2 selective fetch capable.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c          | 8 ++++++++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 2 files changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8261b6455747..34140b2e82ef 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -849,6 +849,7 @@  static const struct intel_device_info jsl_info = {
 	GEN(12), \
 	.display.abox_mask = GENMASK(2, 1), \
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+	.display.has_psr2_sel_fetch = 1, \
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
@@ -890,6 +891,8 @@  static const struct intel_device_info rkl_info = {
 		BIT(TRANSCODER_C),
 	.display.has_hti = 1,
 	.display.has_psr_hw_tracking = 0,
+	/* Wa_16011181250 */
+	.display.has_psr2_sel_fetch = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
 };
@@ -907,6 +910,7 @@  static const struct intel_device_info dg1_info = {
 	.graphics.rel = 10,
 	PLATFORM(INTEL_DG1),
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+	.display.has_psr2_sel_fetch = 0,
 	.require_force_probe = 1,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -921,6 +925,8 @@  static const struct intel_device_info adl_s_info = {
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.display.has_hti = 1,
 	.display.has_psr_hw_tracking = 0,
+	/* Wa_16011181250 */
+	.display.has_psr2_sel_fetch = 0,
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
 	.dma_mask_size = 39,
@@ -1053,6 +1059,8 @@  static const struct intel_device_info dg2_info = {
 	.require_force_probe = 1,
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
+	/* Wa_16011181250 */
+	.display.has_psr2_sel_fetch =  0,
 };
 
 #undef PLATFORM
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..56253b53175e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -169,6 +169,7 @@  enum intel_ppgtt_type {
 	func(has_overlay); \
 	func(has_psr); \
 	func(has_psr_hw_tracking); \
+	func(has_psr2_sel_fetch); \
 	func(overlay_needs_physical); \
 	func(supports_tv);