| Message ID | 20220120235016.1209326-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Introduce G12 subplatform of DG2 | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Matt > Roper > Sent: Thursday, January 20, 2022 3:50 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH] drm/i915: Introduce G12 subplatform of DG2 > > Another fork of the DG2 design has appeared, known as "DG2-G12;" let's > add it as a new subplatform. As with G11, the GT stepping resets back > to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0) > but the display steppings continue to use the same numbering scheme as > G10 and G11. > > Some existing DG2 workarounds are starting to be extended to the DG2-G12 > subplatform. So far only workarounds that were "permanent" for both > DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more > stepping-specific workarounds are likely to show up in the future. > > Bspec: 44477 Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++-------- > drivers/gpu/drm/i915/intel_device_info.h | 3 ++- > drivers/gpu/drm/i915/intel_step.c | 7 +++++++ > 4 files changed, 21 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6a4372c3a3c5..2d2e3ae9c997 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2077,7 +2077,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > } > > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, > STEP_FOREVER) || > - IS_DG2_G11(engine->i915)) { > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) { > /* Wa_22013037850:dg2 */ > wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, > DISABLE_128B_EVICTION_COMMAND_UDW); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 890f1f6fbc49..a2fe5a0a7acd 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1262,6 +1262,8 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) > #define IS_DG2_G11(dev_priv) \ > IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) > +#define IS_DG2_G12(dev_priv) \ > + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) > #define IS_ADLS_RPLS(dev_priv) \ > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, > INTEL_SUBPLATFORM_RPL_S) > #define IS_ADLP_N(dev_priv) \ > @@ -1378,16 +1380,17 @@ IS_SUBPLATFORM(const struct drm_i915_private > *i915, > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) > > /* > - * DG2 hardware steppings are a bit unusual. The hardware design was forked > - * to create two variants (G10 and G11) which have distinct workaround sets. > - * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its > - * first iteration, even though it's more similar to a G10 B0 stepping in terms > - * of functionality and workarounds. However the display stepping does not > - * reset in the same manner --- a specific stepping like "B0" has a consistent > - * meaning regardless of whether it belongs to a G10 or G11 DG2. > + * DG2 hardware steppings are a bit unusual. The hardware design was forked > to > + * create three variants (G10, G11, and G12) which each have distinct > + * workaround sets. The G11 and G12 forks of the DG2 design reset the GT > + * stepping back to "A0" for their first iterations, even though they're more > + * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of > + * functionality and workarounds. However the display stepping does not reset > + * in the same manner --- a specific stepping like "B0" has a consistent > + * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. > * > * TLDR: All GT workarounds and stepping-specific logic must be applied in > - * relation to a specific subplatform (G10 or G11), whereas display workarounds > + * relation to a specific subplatform (G10/G11/G12), whereas display > workarounds > * and stepping-specific logic will be applied with a general DG2-wide stepping > * number. > */ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h > b/drivers/gpu/drm/i915/intel_device_info.h > index 3699b1c539ea..364abcc7aa54 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -96,7 +96,7 @@ enum intel_platform { > * it is fine for the same bit to be used on multiple parent platforms. > */ > > -#define INTEL_SUBPLATFORM_BITS (2) > +#define INTEL_SUBPLATFORM_BITS (3) > #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) > > /* HSW/BDW/SKL/KBL/CFL */ > @@ -109,6 +109,7 @@ enum intel_platform { > /* DG2 */ > #define INTEL_SUBPLATFORM_G10 0 > #define INTEL_SUBPLATFORM_G11 1 > +#define INTEL_SUBPLATFORM_G12 2 > > /* ADL-S */ > #define INTEL_SUBPLATFORM_RPL_S 0 > diff --git a/drivers/gpu/drm/i915/intel_step.c > b/drivers/gpu/drm/i915/intel_step.c > index a4b16b9e2e55..46556883e93d 100644 > --- a/drivers/gpu/drm/i915/intel_step.c > +++ b/drivers/gpu/drm/i915/intel_step.c > @@ -122,6 +122,10 @@ static const struct intel_step_info > dg2_g11_revid_step_tbl[] = { > [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, > }; > > +static const struct intel_step_info dg2_g12_revid_step_tbl[] = { > + [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 }, > +}; > + > void intel_step_init(struct drm_i915_private *i915) > { > const struct intel_step_info *revids = NULL; > @@ -135,6 +139,9 @@ void intel_step_init(struct drm_i915_private *i915) > } else if (IS_DG2_G11(i915)) { > revids = dg2_g11_revid_step_tbl; > size = ARRAY_SIZE(dg2_g11_revid_step_tbl); > + } else if (IS_DG2_G12(i915)) { > + revids = dg2_g12_revid_step_tbl; > + size = ARRAY_SIZE(dg2_g12_revid_step_tbl); > } else if (IS_XEHPSDV(i915)) { > revids = xehpsdv_revids; > size = ARRAY_SIZE(xehpsdv_revids); > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6a4372c3a3c5..2d2e3ae9c997 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2077,7 +2077,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) } if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || - IS_DG2_G11(engine->i915)) { + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) { /* Wa_22013037850:dg2 */ wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DISABLE_128B_EVICTION_COMMAND_UDW); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 890f1f6fbc49..a2fe5a0a7acd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1262,6 +1262,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10) #define IS_DG2_G11(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) +#define IS_DG2_G12(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12) #define IS_ADLS_RPLS(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S) #define IS_ADLP_N(dev_priv) \ @@ -1378,16 +1380,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until)) /* - * DG2 hardware steppings are a bit unusual. The hardware design was forked - * to create two variants (G10 and G11) which have distinct workaround sets. - * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its - * first iteration, even though it's more similar to a G10 B0 stepping in terms - * of functionality and workarounds. However the display stepping does not - * reset in the same manner --- a specific stepping like "B0" has a consistent - * meaning regardless of whether it belongs to a G10 or G11 DG2. + * DG2 hardware steppings are a bit unusual. The hardware design was forked to + * create three variants (G10, G11, and G12) which each have distinct + * workaround sets. The G11 and G12 forks of the DG2 design reset the GT + * stepping back to "A0" for their first iterations, even though they're more + * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of + * functionality and workarounds. However the display stepping does not reset + * in the same manner --- a specific stepping like "B0" has a consistent + * meaning regardless of whether it belongs to a G10, G11, or G12 DG2. * * TLDR: All GT workarounds and stepping-specific logic must be applied in - * relation to a specific subplatform (G10 or G11), whereas display workarounds + * relation to a specific subplatform (G10/G11/G12), whereas display workarounds * and stepping-specific logic will be applied with a general DG2-wide stepping * number. */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 3699b1c539ea..364abcc7aa54 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -96,7 +96,7 @@ enum intel_platform { * it is fine for the same bit to be used on multiple parent platforms. */ -#define INTEL_SUBPLATFORM_BITS (2) +#define INTEL_SUBPLATFORM_BITS (3) #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) /* HSW/BDW/SKL/KBL/CFL */ @@ -109,6 +109,7 @@ enum intel_platform { /* DG2 */ #define INTEL_SUBPLATFORM_G10 0 #define INTEL_SUBPLATFORM_G11 1 +#define INTEL_SUBPLATFORM_G12 2 /* ADL-S */ #define INTEL_SUBPLATFORM_RPL_S 0 diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index a4b16b9e2e55..46556883e93d 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -122,6 +122,10 @@ static const struct intel_step_info dg2_g11_revid_step_tbl[] = { [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, }; +static const struct intel_step_info dg2_g12_revid_step_tbl[] = { + [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 }, +}; + void intel_step_init(struct drm_i915_private *i915) { const struct intel_step_info *revids = NULL; @@ -135,6 +139,9 @@ void intel_step_init(struct drm_i915_private *i915) } else if (IS_DG2_G11(i915)) { revids = dg2_g11_revid_step_tbl; size = ARRAY_SIZE(dg2_g11_revid_step_tbl); + } else if (IS_DG2_G12(i915)) { + revids = dg2_g12_revid_step_tbl; + size = ARRAY_SIZE(dg2_g12_revid_step_tbl); } else if (IS_XEHPSDV(i915)) { revids = xehpsdv_revids; size = ARRAY_SIZE(xehpsdv_revids);
Another fork of the DG2 design has appeared, known as "DG2-G12;" let's add it as a new subplatform. As with G11, the GT stepping resets back to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0) but the display steppings continue to use the same numbering scheme as G10 and G11. Some existing DG2 workarounds are starting to be extended to the DG2-G12 subplatform. So far only workarounds that were "permanent" for both DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more stepping-specific workarounds are likely to show up in the future. Bspec: 44477 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++-------- drivers/gpu/drm/i915/intel_device_info.h | 3 ++- drivers/gpu/drm/i915/intel_step.c | 7 +++++++ 4 files changed, 21 insertions(+), 10 deletions(-)