From patchwork Wed Jan 26 10:48:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 12724937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17746C2BA4C for ; Wed, 26 Jan 2022 10:46:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A17110E808; Wed, 26 Jan 2022 10:46:26 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6DAB410E808 for ; Wed, 26 Jan 2022 10:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643193983; x=1674729983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L0KyIszebexoO5irrh3Mjt+/Tqs03dsOzt13PTJDg9c=; b=CUbqscMo7vMuvj+eYkbu+JzW6BHSQWkvSgQmnpvrGtmnrgE2Z4FbcjyV ugOlYv4bikYLfmBF2lIgv1TNCViiYEren7+d/Orv6grdkA88kLn019Xpc +ea12jN7JgvSW8fji2cOr7swOpfq1A/vSWy62BgaW0MjGsGVJw9gHS5sq 2OAs976jMPH+uT6uAWJG5fy9AGjU/JrRQ25D4ud1LwxVXjg2Ot6ciVWUy EFbdQQhWYtg8Rnn2j7BnErz87jXI5fEzsCd//yEzWJop28S05WTviEMXO AVzmL5siuRunHhW6TApD/Yt0LzxGW+6Gkak89Uk9Cjg39HXaOY1V5JLuJ A==; X-IronPort-AV: E=McAfee;i="6200,9189,10238"; a="246301878" X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="246301878" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2022 02:46:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,317,1635231600"; d="scan'208";a="477445975" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by orsmga003.jf.intel.com with ESMTP; 26 Jan 2022 02:46:22 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Date: Wed, 26 Jan 2022 02:48:17 -0800 Message-Id: <20220126104822.3653079-6-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220126104822.3653079-1-alan.previn.teres.alexis@intel.com> References: <20220126104822.3653079-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 05/10] drm/i915/guc: Add GuC's error state capture output structures. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alan Previn Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add GuC's error capture output structures and definitions as how they would appear in GuC log buffer's error capture subregion after an error state capture G2H event notification. Signed-off-by: Alan Previn Reviewed-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h index a2f97d04ff18..495cdb0228c6 100644 --- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h @@ -28,6 +28,41 @@ struct __guc_mmio_reg_descr_group { struct __guc_mmio_reg_descr *ext; }; +struct guc_state_capture_header_t { + u32 reserved1; + u32 info; + #define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */ + #define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */ + #define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8) + u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */ + u32 guc_id; /* if type-instance, context index of hung context, else set to ~0 */ + u32 num_mmios; + #define CAP_HDR_NUM_MMIOS GENMASK(9, 0) +} __packed; + +struct guc_state_capture_t { + struct guc_state_capture_header_t header; + struct guc_mmio_reg mmio_entries[0]; +} __packed; + +enum guc_capture_group_types { + GUC_STATE_CAPTURE_GROUP_TYPE_FULL, + GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL, + GUC_STATE_CAPTURE_GROUP_TYPE_MAX, +}; + +struct guc_state_capture_group_header_t { + u32 reserved1; + u32 info; + #define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0) + #define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */ +} __packed; + +struct guc_state_capture_group_t { + struct guc_state_capture_group_header_t grp_header; + struct guc_state_capture_t capture_entries[0]; +} __packed; + struct __guc_state_capture_priv { struct __guc_mmio_reg_descr_group *reglists; u16 num_instance_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];