[09/14] drm/i915: Add fdi_m2_n2

Message ID	20220127093303.17309-10-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Jan 2022 11:32:58 +0200 Message-Id: <20220127093303.17309-10-ville.syrjala@linux.intel.com> In-Reply-To: <20220127093303.17309-1-ville.syrjala@linux.intel.com> References: <20220127093303.17309-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 09/14] drm/i915: Add fdi_m2_n2 Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: M/N cleanup \| expand [00/14] drm/i915: M/N cleanup [01/14] drm/i915: Extract intel_{get,set}_m_n() [02/14] drm/i915: Clean up M/N register defines [03/14] drm/i915: s/gmch_{m,n}/data_{m,n}/ [04/14] drm/i915: Move drrs hardware bit frobbing to small helpers [05/14] drm/i915: Make M/N set/get a bit more direct [06/14] drm/i915: Move PCH transcoder M/N setup into the PCH code [07/14] drm/i915: Move M/N setup to a more logical place on ddi platforms [08/14] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() [09/14] drm/i915: Add fdi_m2_n2 [10/14] drm/i915: Program FDI RX TUSIZE2 [11/14] drm/i915: Dump dp_m2_n2 always [12/14] drm/i915: Extract can_enable_drrs() [13/14] drm/i915: Set DP M2/N2 equal to M1/N1 when not doing DRRS [14/14] drm/i915: Always check dp_m2_n2 on pre-bdw

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0a58ecf21b70..8b4d842e2ee0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1815,6 +1815,7 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta if (crtc_state->has_pch_encoder) { intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->fdi_m_n); + intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->fdi_m2_n2); } else if (intel_crtc_has_dp_encoder(crtc_state)) { intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); @@ -3143,8 +3144,8 @@ void intel_set_m_n(struct drm_i915_private *i915, intel_de_write(i915, link_n_reg, m_n->link_n); } -static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, - enum transcoder cpu_transcoder) +bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) { if (IS_HASWELL(dev_priv)) return cpu_transcoder == TRANSCODER_EDP; @@ -3175,7 +3176,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder)) + if (!intel_cpu_transcoder_has_m2_n2(dev_priv, cpu_transcoder)) return; intel_set_m_n(dev_priv, m_n, @@ -3873,7 +3874,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!transcoder_has_m2_n2(dev_priv, cpu_transcoder)) + if (!intel_cpu_transcoder_has_m2_n2(dev_priv, cpu_transcoder)) return; intel_get_m_n(dev_priv, m_n, @@ -5612,10 +5613,14 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, pipe_config->splitter.link_count, pipe_config->splitter.pixel_overlap); - if (pipe_config->has_pch_encoder) - intel_dump_m_n_config(pipe_config, "fdi", + if (pipe_config->has_pch_encoder) { + intel_dump_m_n_config(pipe_config, "fdi m_n", pipe_config->fdi_lanes, &pipe_config->fdi_m_n); + intel_dump_m_n_config(pipe_config, "fdi m2_n2", + pipe_config->fdi_lanes, + &pipe_config->fdi_m2_n2); + } if (intel_crtc_has_dp_encoder(pipe_config)) { intel_dump_m_n_config(pipe_config, "dp m_n", @@ -6467,6 +6472,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(has_pch_encoder); PIPE_CONF_CHECK_I(fdi_lanes); PIPE_CONF_CHECK_M_N(fdi_m_n); + PIPE_CONF_CHECK_M_N(fdi_m2_n2); PIPE_CONF_CHECK_I(lane_count); PIPE_CONF_CHECK_X(lane_lat_optim_mask); @@ -7375,6 +7381,7 @@ static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_stat * FIXME: should really copy more fuzzy state here */ new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; + new_crtc_state->fdi_m2_n2 = old_crtc_state->fdi_m2_n2; new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; new_crtc_state->has_drrs = old_crtc_state->has_drrs; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index afa312e11624..71a27285cf99 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -575,6 +575,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, enum transcoder cpu_transcoder, struct intel_link_m_n *m_n); +bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder); void intel_plane_destroy(struct drm_plane *plane); void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 60e15226a8cb..4f29146b916e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1124,7 +1124,7 @@ struct intel_crtc_state { /* FDI configuration, only valid if has_pch_encoder is set. */ int fdi_lanes; - struct intel_link_m_n fdi_m_n; + struct intel_link_m_n fdi_m_n, fdi_m2_n2; bool ips_enabled; diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 3d6e22923601..fdbeaf6f38f4 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -251,6 +251,9 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, link_bw, &pipe_config->fdi_m_n, false, false); + if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) + pipe_config->fdi_m2_n2 = pipe_config->fdi_m_n; + ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config); if (ret == -EDEADLK) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 9192769e3337..69b8a4e77c71 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -436,6 +436,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, &crtc_state->fdi_m_n); + intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m2_n2); if (HAS_PCH_IBX(dev_priv)) { /*

[09/14] drm/i915: Add fdi_m2_n2

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