[v2,05/17] drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants

Message ID	20220128103757.22461-6-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jan 2022 12:37:45 +0200 Message-Id: <20220128103757.22461-6-ville.syrjala@linux.intel.com> In-Reply-To: <20220128103757.22461-1-ville.syrjala@linux.intel.com> References: <20220128103757.22461-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH v2 05/17] drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: M/N cleanup \| expand [v2,00/17] drm/i915: M/N cleanup [v2,01/17] drm/i915: Nuke intel_dp_set_m_n() [v2,02/17] drm/i915: Nuke intel_dp_get_m_n() [v2,03/17] drm/i915: Nuke ilk_get_fdi_m_n_config() [v2,04/17] drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants [v2,05/17] drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants [v2,06/17] drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() [v2,07/17] drm/i915: Move PCH transcoder M/N setup into the PCH code [v2,08/17] drm/i915: Move M/N setup to a more logical place on ddi platforms [v2,09/17] drm/i915: Extract {i9xx, ilk}_configure_cpu_transcoder() [v2,10/17] drm/i915: Disable DRRS on IVB/HSW port != A [v2,11/17] drm/i915: Extract can_enable_drrs() [v2,12/17] drm/i915: Fix intel_cpu_transcoder_has_m2_n2() [v2,13/17] drm/i915: Clear DP M2/N2 when not doing DRRS [v2,14/17] drm/i915: Program pch transcoder m2/n2 [v2,15/17] drm/i915: Dump dp_m2_n2 always [v2,16/17] drm/i915: Always check dp_m2_n2 on pre-bdw [v2,17/17] drm/i915: Document BDW+ DRRS M/N programming requirements

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 771bff714772..07432f6b56ac 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -337,12 +337,14 @@ static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - if (crtc_state->has_pch_encoder) + if (crtc_state->has_pch_encoder) { intel_pch_transcoder_get_m_n(crtc, &crtc_state->dp_m_n); - else - intel_cpu_transcoder_get_m_n(crtc, crtc_state->cpu_transcoder, - &crtc_state->dp_m_n, - &crtc_state->dp_m2_n2); + } else { + intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, + &crtc_state->dp_m_n); + intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, + &crtc_state->dp_m2_n2); + } } static void intel_dp_get_config(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index dead4b72719f..b02b327331f8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3362,9 +3362,10 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->lane_count = ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; - intel_cpu_transcoder_get_m_n(crtc, cpu_transcoder, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); + intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, + &pipe_config->dp_m_n); + intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, + &pipe_config->dp_m2_n2); if (DISPLAY_VER(dev_priv) >= 11) { i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); @@ -3401,9 +3402,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, pipe_config->mst_master_transcoder = REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); - intel_cpu_transcoder_get_m_n(crtc, cpu_transcoder, - &pipe_config->dp_m_n, - &pipe_config->dp_m2_n2); + intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, + &pipe_config->dp_m_n); pipe_config->infoframes.enable |= intel_hdmi_infoframes_enabled(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 13355e8778f8..79f22a3f2e20 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3877,29 +3877,35 @@ void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } -void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, - enum transcoder transcoder, - struct intel_link_m_n *m_n, - struct intel_link_m_n *m2_n2) +void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, + enum transcoder transcoder, + struct intel_link_m_n *m_n) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (DISPLAY_VER(dev_priv) >= 5) { + if (DISPLAY_VER(dev_priv) >= 5) intel_get_m_n(dev_priv, m_n, PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); - - if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { - intel_get_m_n(dev_priv, m2_n2, - PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), - PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); - } - } else { + else intel_get_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); - } +} + +void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, + enum transcoder transcoder, + struct intel_link_m_n *m_n) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + if (!transcoder_has_m2_n2(dev_priv, transcoder)) + return; + + intel_get_m_n(dev_priv, m_n, + PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), + PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); } static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 036e28581019..9a232bdef0f2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -608,10 +608,12 @@ void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state, const struct intel_link_m_n *m_n); void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state, const struct intel_link_m_n *m_n); -void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, - enum transcoder cpu_transcoder, - struct intel_link_m_n *m_n, - struct intel_link_m_n *m2_n2); +void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, + enum transcoder cpu_transcoder, + struct intel_link_m_n *m_n); +void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, + enum transcoder cpu_transcoder, + struct intel_link_m_n *m_n); void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, struct intel_link_m_n *m_n); void i9xx_crtc_clock_get(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index b464633b551b..dd010be534a2 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -386,8 +386,8 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; - intel_cpu_transcoder_get_m_n(crtc, crtc_state->cpu_transcoder, - &crtc_state->fdi_m_n, NULL); + intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n); if (HAS_PCH_IBX(dev_priv)) { /* @@ -510,8 +510,8 @@ void lpt_pch_get_config(struct intel_crtc_state *crtc_state) crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; - intel_cpu_transcoder_get_m_n(crtc, crtc_state->cpu_transcoder, - &crtc_state->fdi_m_n, NULL); + intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, + &crtc_state->fdi_m_n); crtc_state->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); }

[v2,05/17] drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variants

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Patch