| Message ID | 20220128185209.18077-2-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Misc DG2 enabling patches | expand |
On Fri, 28 Jan 2022 at 18:52, Ramalingam C <ramalingam.c@intel.com> wrote: > > An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs > restore hang during context restore of a preempted context in GPGPU mode > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > cc: Chris Wilson <chris.p.wilson@intel.com> Acked-by: Matthew Auld <matthew.auld@intel.com>
On 07/02/2022 11:48, Matthew Auld wrote: > On Fri, 28 Jan 2022 at 18:52, Ramalingam C <ramalingam.c@intel.com> wrote: >> >> An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs >> restore hang during context restore of a preempted context in GPGPU mode >> >> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> >> cc: Chris Wilson <chris.p.wilson@intel.com> > Acked-by: Matthew Auld <matthew.auld@intel.com> Also, feel free to upgrade to r-b for this and patches 2-4.
On 2022-02-07 at 11:52:48 +0000, Matthew Auld wrote: > On 07/02/2022 11:48, Matthew Auld wrote: > > On Fri, 28 Jan 2022 at 18:52, Ramalingam C <ramalingam.c@intel.com> wrote: > > > > > > An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs > > > restore hang during context restore of a preempted context in GPGPU mode > > > > > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > > > cc: Chris Wilson <chris.p.wilson@intel.com> > > Acked-by: Matthew Auld <matthew.auld@intel.com> > > Also, feel free to upgrade to r-b for this and patches 2-4. Thank you Matt. I have pushed these changes to the tree. Ram.
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 89a95a125fc8..8440f4b0f613 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1165,6 +1165,29 @@ gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs) return cs; } +/* + * On DG2 during context restore of a preempted context in GPGPU mode, + * RCS restore hang is detected. This is extremely timing dependent. + * To address this below sw wabb is implemented for DG2 A steppings. + */ +static u32 * +dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs) +{ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG); + *cs++ = 0x21; + + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base)); + *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT1); + + *cs++ = MI_LOAD_REGISTER_REG; + *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base)); + *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT2); + + return cs; +} + static u32 * gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) { @@ -1172,6 +1195,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs); + /* Wa_22011450934:dg2 */ + if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) || + IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0)) + cs = dg2_emit_rcs_hang_wabb(ce, cs); + /* Wa_16013000631:dg2 */ if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || IS_DG2_G11(ce->engine->i915)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ec48406eb37a..3f94f4b5ef6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -12026,4 +12026,8 @@ enum skl_power_gate { #define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731C) #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) +#define GEN12_CULLBIT1 _MMIO(0x6100) +#define GEN12_CULLBIT2 _MMIO(0x7030) +#define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) + #endif /* _I915_REG_H_ */
An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs restore hang during context restore of a preempted context in GPGPU mode Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Chris Wilson <chris.p.wilson@intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 32 insertions(+)