| Message ID | 20220128221020.188253-2-michael.cheng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use drm_clflush* instead of clflush | expand |
> -----Original Message----- > From: Cheng, Michael <michael.cheng@intel.com> > Sent: Friday, January 28, 2022 2:10 PM > To: intel-gfx@lists.freedesktop.org > Cc: Cheng, Michael <michael.cheng@intel.com>; Bowman, Casey G > <casey.g.bowman@intel.com>; De Marchi, Lucas > <lucas.demarchi@intel.com>; Boyer, Wayne <wayne.boyer@intel.com>; > ville.syrjala@linux.intel.com; Kuoppala, Mika <mika.kuoppala@intel.com>; > Auld, Matthew <matthew.auld@intel.com> > Subject: [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page > > Re-work intel_write_status_page to use drm_clflush_virt_range. This will > prevent compiler errors when building for non-x86 architectures. > > Signed-off-by: Michael Cheng <michael.cheng@intel.com> Reviewed-by: Casey Bowman <casey.g.bowman@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h > b/drivers/gpu/drm/i915/gt/intel_engine.h > index 08559ace0ada..beb979e40a13 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -4,6 +4,7 @@ > > #include <asm/cacheflush.h> > #include <drm/drm_util.h> > +#include <drm/drm_cache.h> > > #include <linux/hashtable.h> > #include <linux/irq_work.h> > @@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs > *engine, int reg, u32 value) > * of extra paranoia to try and ensure that the HWS takes the value > * we give and that it doesn't end up trapped inside the CPU! > */ > - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { > - mb(); > - clflush(&engine->status_page.addr[reg]); > - engine->status_page.addr[reg] = value; > - clflush(&engine->status_page.addr[reg]); > - mb(); > - } else { > - WRITE_ONCE(engine->status_page.addr[reg], value); > - } > + drm_clflush_virt_range(&engine->status_page.addr[reg], > sizeof(value)); > + WRITE_ONCE(engine->status_page.addr[reg], value); > + drm_clflush_virt_range(&engine->status_page.addr[reg], > sizeof(value)); > } > > /* > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 08559ace0ada..beb979e40a13 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@ #include <asm/cacheflush.h> #include <drm/drm_util.h> +#include <drm/drm_cache.h> #include <linux/hashtable.h> #include <linux/irq_work.h> @@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); } /*
Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-)