From patchwork Fri Jan 28 22:10:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12729154 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05587C433F5 for ; Fri, 28 Jan 2022 22:10:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A920910E142; Fri, 28 Jan 2022 22:10:28 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 84BEC10E12F for ; Fri, 28 Jan 2022 22:10:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643407827; x=1674943827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6JVP7jlLFCQi1nnUdnNA3/51TnuVcQYN602hxvTxyho=; b=lpO03vEQBmNbXdAhvi9ouaoOsaag7+DCD9CrUr+qUhtMNeYmN7RdHoSJ zDfpk9kGQi3HFLknnVZa1Ji2PLXeCOugzS4Ne9xsVFk8VbhnCLneUI6XJ 4iSVbyxhSXG6zxWm2oeuhMNbTFh3sXJbwqSYXU07Z831/eNlSL+L+CZ43 Hn6Y3Zf8TK+yG7/wr6Z5VaPR+1pYr+vm9mHuBRIBt5vO6LfTcfHsZCNR6 UaGnyIY+b5Gc8G6zZTGwda97cRuwqS6FU5/fgbnOpZB4KcJUOVE3YCLeK 0+U+4YvhJZhYakvmW1SBACwTM/8zMyK1vx9VkJhURXDhfvMF089wthIfA A==; X-IronPort-AV: E=McAfee;i="6200,9189,10241"; a="247155718" X-IronPort-AV: E=Sophos;i="5.88,325,1635231600"; d="scan'208";a="247155718" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 14:10:27 -0800 X-IronPort-AV: E=Sophos;i="5.88,325,1635231600"; d="scan'208";a="496265919" Received: from bainsko-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.109.18]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jan 2022 14:10:26 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jan 2022 14:10:17 -0800 Message-Id: <20220128221020.188253-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128221020.188253-1-michael.cheng@intel.com> References: <20220128221020.188253-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, matthew.auld@intel.com, mika.kuoppala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng Reviewed-by: Casey Bowman --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 08559ace0ada..beb979e40a13 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); } /*