| Message ID | 20220210012617.1061641-2-michael.cheng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use drm_clflush* instead of clflush | expand |
On 10/02/2022 01:26, Michael Cheng wrote: > Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc > performs a flush by first performing a clean, follow by an invalidation > operation. > > v2 (Michael Cheng): Use correct macro for cleaning and invalidation the > dcache. > > v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h > > v4 (Michael Cheng): Rebase > > Signed-off-by: Michael Cheng <michael.cheng@intel.com> > --- > drivers/gpu/drm/drm_cache.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > index 66597e411764..ec8d91b088ff 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -28,6 +28,7 @@ > * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> > */ > > +#include <asm/cacheflush.h> I thought linux/cacheflush.h would be correct. Regards, Tvrtko > #include <linux/cc_platform.h> > #include <linux/export.h> > #include <linux/highmem.h> > @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) > > if (wbinvd_on_all_cpus()) > pr_err("Timed out waiting for cache flush\n"); > + > +#elif defined(CONFIG_ARM64) > + void *end = addr + length; > + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); > #else > WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); > #endif
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 66597e411764..ec8d91b088ff 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> */ +#include <asm/cacheflush.h> #include <linux/cc_platform.h> #include <linux/export.h> #include <linux/highmem.h> @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h v4 (Michael Cheng): Rebase Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)