From patchwork Thu Feb 10 01:26:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4660CC433FE for ; Thu, 10 Feb 2022 01:26:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D79C10E6C5; Thu, 10 Feb 2022 01:26:24 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id A02C510E3C4; Thu, 10 Feb 2022 01:26:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644456381; x=1675992381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uTZRO8AL3pt7KalgtHlKIDcizA+L2CcZP0n/RbxAfrs=; b=cy2SjyZJsYMsfGZaj9FSGmO8kAkrCzsJ4Tc+kNCycN4oujpf1pQgrXi7 X81H/D2YPf1M2r7i0gcVN/VcElF2ZD/i5CXOdmWHymOKQueiLS+NyZLSM 6zStxA2GK5/m750XdYmnjDcZ9GJqGykkF3mbaaSMN3wVtnFPXmz6zi/SO FkuTEONYR0FfjMXxk9CmDFjVSlXBuop4W1OUMXGnRpqp1Cp7HPwJLINxa 5+9AP4ws1sRAFvog/FQIVYIr/UOxtxmxUhJbbNBOtDz1o7SKf4sAAnt5g UL2Zi/Xp5Ec3WX/gxSqF7KCcOx3lOuGo57IxOtwtoxpvFjmKDX6d2Xmc7 w==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="249591577" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="249591577" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 17:26:21 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="773706166" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 17:26:21 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 17:26:12 -0800 Message-Id: <20220210012617.1061641-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210012617.1061641-1-michael.cheng@intel.com> References: <20220210012617.1061641-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h v4 (Michael Cheng): Rebase Signed-off-by: Michael Cheng --- drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 66597e411764..ec8d91b088ff 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström */ +#include #include #include #include @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif