From patchwork Thu Feb 10 01:26:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12741105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EA1CC4332F for ; Thu, 10 Feb 2022 01:26:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAE8710E6D7; Thu, 10 Feb 2022 01:26:24 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3249310E3C4; Thu, 10 Feb 2022 01:26:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644456383; x=1675992383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n5RKJcp81B88J6tTgVRUp4ooYKldFrNbNiKg6W8kZms=; b=R2sgW6crPKj9/GLZcvWUxGm1su5czT8WaRbEBWSwZgwto81oFqisMxoq 1InE+9Mh2i5UAmmcFq5yJy0Yz85QxDb3p80bJ/WZjDYGvVMg2dKbl0PJl Fnt9jok8XsM68D9oZ9sZ+xgcCOLOu8lwL1y0IBxnSpaKnpr7FETwZC+f7 9js/riU+d71HRfFpS7B64Ns/Q7ENmVMLtfz1vNPaaRukxU+Zg6K8rr6WE 2/OHTqlxCR8domoM1RdZ/44CRcugC34Z+UDEYVIrQbZ3g6ceTiabVVDow Vw4xjtxKrx+7hhclitUQlqcBo1asZvCY1VuilT5x30igaaaJ8h+vsbYoJ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10253"; a="249591584" X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="249591584" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 17:26:23 -0800 X-IronPort-AV: E=Sophos;i="5.88,357,1635231600"; d="scan'208";a="773706180" Received: from sroy1-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.209.85.186]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2022 17:26:22 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Feb 2022 17:26:15 -0800 Message-Id: <20220210012617.1061641-5-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210012617.1061641-1-michael.cheng@intel.com> References: <20220210012617.1061641-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 4/6] drm/i915/gt: Re-work reset_csb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures. v2(Michael Cheng): Remove extra clflush v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 28f2581d3046..cc561cfae808 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists; - mb(); /* paranoia: read the CSB pointers from after the reset */ - clflush(execlists->csb_write); - mb(); + drm_clflush_virt_range(execlists->csb_write, + sizeof(execlists->csb_write)); inactive = process_csb(engine, inactive); /* drain preemption events */