From patchwork Thu Feb 10 18:36:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Cheng X-Patchwork-Id: 12742287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4680CC4332F for ; Thu, 10 Feb 2022 18:37:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E518110E94E; Thu, 10 Feb 2022 18:36:55 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94E5110E95E; Thu, 10 Feb 2022 18:36:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644518212; x=1676054212; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=faWa0zkc3IIPb1B1W8H3JVxgoY3eN/wvxr92/FnXeH8=; b=FkV0EVovNOWg06wW17D/6r4FX9xCi590Gr6ofkkc0Q4WG9J1fIfz5CXo eJVat3aVeO9OY84tswNghyBzXRaknSuCsvaCHlXbwEPWkCicUQZzg/DtR EKTUwVOlit4m7CTaGTeFCURPB6P2N1KTDg13i9XMuvqWS5/Ml1tiM0gE/ JTmvFkfhVZlykHEe57apGmqf1rOoAwEhbiqc1TH5Bzkf3QTU6Jvh4vA4z YYJ/6rSEN2ICHK91sMM920dvqYYTIUigfmB771MjZtl5DIZDaE9MNijEZ D7qKmmi5tYykZFk5v6J0h7zivl1AbT+K4kLREOliq1viHLQPp/arTZmnH g==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="229528162" X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="229528162" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 X-IronPort-AV: E=Sophos;i="5.88,359,1635231600"; d="scan'208";a="526616757" Received: from lmoua-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.212.169.226]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 10:36:40 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Thu, 10 Feb 2022 10:36:31 -0800 Message-Id: <20220210183636.1187973-2-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220210183636.1187973-1-michael.cheng@intel.com> References: <20220210183636.1187973-1-michael.cheng@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v10 1/6] drm: Add arch arm64 for drm_clflush_virt_range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc performs a flush by first performing a clean, follow by an invalidation operation. v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h v4 (Michael Cheng): Rebase v5 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h Signed-off-by: Michael Cheng Reviewed-by: Matt Roper --- drivers/gpu/drm/drm_cache.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 66597e411764..2e233f53331e 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -28,6 +28,7 @@ * Authors: Thomas Hellström */ +#include #include #include #include @@ -174,6 +175,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end); + #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif