| Message ID | 20220210183636.1187973-3-michael.cheng@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use drm_clflush* instead of clflush | expand |
On Thu, Feb 10, 2022 at 10:36:32AM -0800, Michael Cheng wrote: > Re-work intel_write_status_page to use drm_clflush_virt_range. This > will prevent compiler errors when building for non-x86 architectures. > It looks like this will also cause old x86 cpu's that don't have clflush to do an extra wbinvd that they didn't do before; based on commit 9a29dd85a09d ("drm/i915: Fixup intel_write_status_page() for old CPUs without clflush") we were just hoping that they were sufficiently coherent that we can get away without extra flushing. As far as I can see, this function is only used from a selftest, not from real driver codepaths, so the extra flushing shouldn't have any negative impact on end users. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Michael Cheng <michael.cheng@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 0e353d8c2bc8..986777c2430d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -4,6 +4,7 @@ > > #include <asm/cacheflush.h> > #include <drm/drm_util.h> > +#include <drm/drm_cache.h> > > #include <linux/hashtable.h> > #include <linux/irq_work.h> > @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) > * of extra paranoia to try and ensure that the HWS takes the value > * we give and that it doesn't end up trapped inside the CPU! > */ > - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { > - mb(); > - clflush(&engine->status_page.addr[reg]); > - engine->status_page.addr[reg] = value; > - clflush(&engine->status_page.addr[reg]); > - mb(); > - } else { > - WRITE_ONCE(engine->status_page.addr[reg], value); > - } > + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); > + WRITE_ONCE(engine->status_page.addr[reg], value); > + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); > } > > /* > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index 0e353d8c2bc8..986777c2430d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@ #include <asm/cacheflush.h> #include <drm/drm_util.h> +#include <drm/drm_cache.h> #include <linux/hashtable.h> #include <linux/irq_work.h> @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); } /*
Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures. Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-)